Equalization training method and apparatus, and system

Patent metadata

Field	Value
Publication number	US-12095597-B2
Application number	US-202218070986-A
Country	US
Kind code	B2
Filing date	Nov 29, 2022
Priority date	May 30, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase. According to this method, an equalization timeout period used for equalization training can be flexibly configured for each equalization training process, so that the configured equalization timeout period better conforms to a training rate currently used for link negotiation, to better ensure that an equalization parameter is found within the configured equalization timeout period, thereby improving an equalization training success rate.

First claim

What is claimed is:

1. An equalization training method, comprising:
obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and
determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
equalization training in the target phase is performed on the master chip and the slave chip within the equalization timeout period in the target phase.

2. The method according to claim 1 , wherein when the target rate threshold interval is a threshold interval comprising a minimum rate in the N+1 rate threshold intervals, the target equalization timeout period is a forward compatible equalization timeout period.

3. The method according to claim 1 , wherein the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods is prestored in a register of the master chip or in a register of the slave chip.

4. The method according to claim 1 , wherein the master chip and the slave chip are connected through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus, the master chip is a root complex or a switch chip, and the slave chip is an endpoint device independent of the master chip.

5. An equalization training apparatus, comprising:
a transceiver, configured to obtain a training rate of each of a master chip and a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and
a manager, configured to: determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
equalization training in the target phase is performed on the master chip and the slave chip within the equalization timeout period in the target phase.

6. The apparatus according to claim 5 , wherein when the target rate threshold interval is a threshold interval comprising a minimum rate in the N+1 rate threshold intervals, the target equalization timeout period is a forward compatible equalization timeout period.

7. The apparatus according to claim 5 , wherein the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods is prestored in a register of the master chip or in a register of the slave chip.

8. The apparatus according to claim 5 , wherein the master chip and the slave chip are connected through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus, the master chip is a root complex or a switch chip, and the slave chip is an endpoint device independent of the master chip.

9. A chip, comprising:
a register, configured to store a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods;
a transceiver, configured to obtain a training rate of each of a master chip and a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and
a manager, configured to: determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
equalization training in the target phase is performed on the master chip and the slave chip within the equalization timeout period in the target phase.

10. The chip according to claim 9 , wherein when the target rate threshold interval is a threshold interval comprising a minimum rate in the N+1 rate threshold intervals, the target equalization timeout period is a forward compatible equalization timeout period.

11. The chip according to claim 9 , wherein the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods is prestored in a register of the master chip or in a register of the slave chip.

12. A communications system, comprising:
a processing system configured to execute system software;
a master chip;
a slave chip;
wherein the master chip and the slave chip are connected to each other through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus; and
wherein the processing system executes the system software to configured the processing system to:
obtain a training rate of each of a master chip and a slave chip in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and
determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
equalization training in the target phase is performed on the master chip and the slave chip within the equalization timeout period in the target phase.

13. The communications system according to claim 12 , further comprising:
a memory, configured to store the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods.

14. The communications system according to claim 12 , wherein when the target rate threshold interval is a threshold interval comprising a minimum rate in the N+1 rate threshold intervals, the target equalization timeout period is a forward compatible equalization timeout period.

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Yongyao
• Luo Fei
• Zhu Jiang

Classifications

• H04B3/04

  Control of transmission; Equalising · CPC title

• H04L25/03885 Primary

  adaptive · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title