Equalization time configuration method, chip, and communications system

Patent metadata

Field	Value
Publication number	US-11921660-B2
Application number	US-202217827271-A
Country	US
Kind code	B2
Filing date	May 27, 2022
Priority date	May 23, 2018
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

First claim

What is claimed is:

1. An equalization time configuration method comprising:
obtaining a port number of a master chip and an identity of a slave chip;
obtaining, based on the port number and the identity, a channel type of a channel between a port of the master chip and the slave chip, wherein the channel type is long reach (LR) or short reach (SR);
obtaining a first physical layer (PHY) type supported by the master chip and a second PHY type supported by the slave chip;
determining whether both the first PHY type and the second PHY type comprise the channel type;
determining a first working PHY type of the master chip and a second working PHY type of the slave chip when both the first PHY type and the second PHY type comprise the channel type, wherein both the first working PHY type and the second working PHY type are the channel type;
configuring a first equalization time of the master chip in a third phase of an equalization based on the second working PHY type; and
configuring a second equalization time of the slave chip in a fourth phase of the equalization based on the first working PHY type.

2. The equalization time configuration method of claim 1 , further comprising:
configuring a first equalization circuit of the slave chip based on the second working PHY type;
determining, based on the first equalization circuit, a third equalization time required by the slave chip in the third phase; and
configuring the first equalization time based on the third equalization time.

3. The equalization time configuration method of claim 1 , further comprising:
configuring a second equalization circuit of the master chip based on the first working PHY type;
determining, based on the second equalization circuit, a third equalization time required by the master chip in the fourth phase; and
configuring the second equalization time based on the third equalization time.

4. The equalization time configuration method of claim 1 , wherein the first equalization time is T1 when the second working PHY type is the SR, wherein the first equalization time is T2 when the second working PHY type is the LR, and wherein T2 is greater than T1.

5. The equalization time configuration method of claim 1 , wherein the second equalization time is T3 when the first working PHY type is the SR, wherein the second equalization time is T4 when the first working PHY type is the LR, and wherein T4 is greater than T3.

6. The equalization time configuration method of claim 1 , further comprising:
when both the first working PHY type and the second working PHY type are the LR:
reading a third equalization time of the slave chip in the third phase;
writing the third equalization time into the master chip to set the third equalization time as the first equalization time;
reading a fourth equalization time of the master chip in the fourth phase; and
writing the fourth equalization time into the slave chip to set the fourth equalization time as the second equalization time; and

configuring both the first equalization time and the second equalization time as a default value when both the first working PHY type and the second working PHY type are the SR.

7. The equalization time configuration method of claim 1 , further comprising:
when both the first working PHY type and the second working PHY type are SR:
reading a third equalization time of the slave chip in the third phase;
writing the third equalization time into the master chip to set the third equalization time as the first equalization time;
reading a fourth equalization time of the master chip in the fourth phase; and
writing the fourth equalization time into the slave chip to set the fourth equalization time as the second equalization time; and

configuring both the first equalization time and the second equalization time as a default value when both the first working PHY type and the second working PHY type are the LR.

8. The equalization time configuration method of claim 1 , wherein the master chip and the slave chip are coupled to each other using a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus, wherein the master chip is a root complex or a switching chip, and wherein the slave chip is an endpoint device independent of the master chip.

9. The equalization time configuration method of claim 1 , further comprising obtaining the channel type based on a loss of the channel, wherein a first channel loss corresponding to the LR is greater than a second channel loss corresponding to the SR.

10. The equalization time configuration method of claim 1 , wherein the first PHY type supported by the master chip is based on a first channel loss that the master chip is able to drive, wherein the second PHY type supported by the slave chip is based on a second channel loss that the slave chip is able to drive, wherein the first channel loss is greater when the first PHY type is the LR than when the first PHY type is the SR, and wherein the second channel loss is greater when the second PHY type is the LR than when the second PHY type is the SR.

11. The equalization time configuration method of claim 1 , further comprising:
storing the first PHY type in a first register of the master chip; and
storing the second PHY type in a second register of the slave chip.

12. An equalization time configuration apparatus comprising:
a transceiver configured to:
receive a port number of a master chip and an identity of a slave chip; and
receive a first physical layer (PHY) type supported by the master chip and a second PHY type supported by the slave chip; and

a processor coupled to the transceiver and configured to:
determine, based on the port number and the identity, a channel type of a channel between a port of the master chip and the slave chip, wherein the channel type is long reach (LR) or short reach (SR);
determine whether both the first PHY type and the second PHY type comprise the channel type;

determine a first working PHY type of the master chip and a second working PHY type of the slave chip when both the first PHY type and the second PHY type comprise the channel type, wherein both the first working PHY type and the second working PHY type are the channel type;
configure a first equalization time of the master chip in a third phase of an equalization based on the second working PHY type; and
configure a second equalization time of the slave chip in a fourth phase of the equalization based on the first working PHY type.

13. The equalization time configuration apparatus of claim 12 , wherein the processor is further configured to configure the first equalization time based on a third equalization time required by the slave chip in the third phase, wherein the third equalization time is based on a first equalization circuit of the slave chip, and wherein the first equalization circuit is based on the second working PHY type.

14. The equalization time configuration apparatus of claim 12 , wherein the processor is further configured to configure the second equalization time based on a third equalization time required by the master chip in the fourth phase, wherein the third equalization time is based on a second equalization circuit of the master chip, and wherein the second equalization circuit is based on the first working PHY type.

15. The equalization time configuration apparatus of claim 12 , wherein the processor is further configured to:
configure both the first equalization time and the second equalization time as a default value when both the first working PHY type and the second working PHY t

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Yongyao
• Zhu Jiang
• Luo Fei
• Li Jiankang
• Ma Yulong

Classifications

• G06F13/362 Primary

  with centralised access control · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F8/71 Primary

  Version control (security arrangements therefor G06F21/57); Configuration management · CPC title

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title