Semiconductor devices and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12094974-B2
Application number	US-202318307279-A
Country	US
Kind code	B2
Filing date	Apr 26, 2023
Priority date	Jul 3, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a stack structure by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers on an active region of a substrate;
forming a fin-shaped structure on the active region by partially etching the stack structure, the fin-shaped structure extending in a first direction parallel to an upper surface of the substrate;
forming a silicon epitaxial liner on a surface of the fin-shaped structure;
forming a gap-fill insulating film on the silicon epitaxial liner to surround the fin-shaped structure;
applying an annealing process to the gap-fill insulating film; and
partially removing the gap-fill insulating film to expose the fin-shaped structure.

2. The method of claim 1 , further comprising:
applying a nitriding treatment process using plasma to the silicon epitaxial liner between the forming of the silicon epitaxial liner and the forming of the gap-fill insulating film.

3. The method of claim 1 , further comprising:
repeating the forming of the gap-fill insulating film and the applying the annealing process, prior to the partially removing of the gap-fill insulating film.

4. The method of claim 1 , wherein the forming of the fin-shaped structure includes:
sequentially forming a buffer oxide layer and a mask layer on a region corresponding to the fin-shaped structure, and
etching the stack structure using the mask layer such that the buffer oxide layer is partially etched to expose an edge region of an upper surface of the fin-shaped structure.

5. The method of claim 4 , wherein in the forming of the silicon epitaxial liner, a silicon epitaxial portion is formed on the edge region of the upper surface of the fin-shaped structure.

6. The method of claim 1 , wherein the forming of the silicon epitaxial liner is performed in a range of 300° C. to 700° C.

7. The method of claim 1 , wherein the annealing process is a wet annealing process.

8. The method of claim 1 , wherein a thickness of the silicon epitaxial liner increases after the annealing process.

9. The method of claim 1 , wherein widths of the plurality of first semiconductor layers are reduced to be less than widths of the plurality of second semiconductor layers in the annealing process.

10. The method of claim 1 , wherein the plurality of second semiconductor layers includes an uppermost semiconductor layer, a lowermost semiconductor layer, and an intermediate semiconductor layer between the uppermost semiconductor layer and the lowermost semiconductor layer, and
wherein after the annealing process, the uppermost semiconductor layer has a width greater than a width of the intermediate semiconductor layer in a cross section taken in a second direction, the second direction parallel to the upper surface of the substrate and intersecting the first direction.

11. The method of claim 10 , wherein after the annealing process, the width of the intermediate semiconductor layer is less than a width of the lowermost semiconductor layer in the cross section taken in the second direction.

12. The method of claim 10 , wherein after the annealing process, the uppermost semiconductor layer has downwardly inclined side surfaces in the cross section taken in the second direction.

13. The method of claim 10 , wherein after the annealing process, the lowermost semiconductor layer has upwardly inclined side surfaces in the cross section taken in the second direction.

14. The method of claim 10 , wherein after the annealing process both side surfaces of the intermediate semiconductor layer have a convex shape in the cross section taken in the second direction.

15. The method of claim 1 , wherein each of the plurality of first semiconductor layers includes SiGe, and each of the plurality of second semiconductor layers includes Si.

16. A method of fabricating a semiconductor device, comprising:
forming a stack structure by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers on an active region of a substrate;
forming a fin-shaped structure on the active region by partially etching the stack structure, the fin-shaped structure extending in a first direction parallel to an upper surface of the substrate;
forming a silicon epitaxial liner on a surface of the fin-shaped structure;
forming a gap-fill insulating film on the silicon epitaxial liner to surround the fin-shaped structure;
applying an annealing process to the gap-fill insulating film;
partially removing the gap-fill insulating film to expose the fin-shaped structure;
forming a dummy gate electrode extending in a second direction on the fin-shaped structure, the second direction parallel to the upper surface of the substrate and intersecting the first direction;
forming gate spacers on both sidewalls of the dummy gate electrode;
forming a recess in a portion of the fin-shaped structure on at least one side of the dummy gate electrode;
forming a source/drain region in the recess of the fin-shaped structure;
removing the dummy gate electrode between the gate spacers;
selectively removing the plurality of first semiconductor layers from the fin-shaped structure; and
sequentially forming a gate insulating film and a gate electrode between the gate spacers to surrounding each of the plurality of second semiconductor layers in the second direction.

17. The method of claim 16 , wherein the plurality of second semiconductor layers includes an uppermost semiconductor layer, a lowermost semiconductor layer, and an intermediate semiconductor layer between the uppermost semiconductor layer and the lowermost semiconductor layer, and
wherein, after the annealing process, the intermediate semiconductor layer has a width less than a width of the lowermost semiconductor layer in the second direction.

18. The method of claim 17 , wherein after the annealing process, the width of the intermediate semiconductor layer is less than a width of the uppermost semiconductor layer in a cross section taken in the second direction.

19. The method of claim 18 , wherein after the annealing process, a difference in the width of the intermediate semiconductor layer and the width of the uppermost semiconductor layer is in a range of 1 nm to 10 nm in the cross section taken in the second direction.

20. A method of fabricating a semiconductor device, comprising:
forming a stack structure by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers on an active region of a substrate;
sequentially forming a mask pattern on the stack structure, the mask pattern extending in a first direction parallel to an upper surface of the substrate;
etching the stack structure using the mask pattern to form a fin-shaped structure extending in the first direction on the active region;
conformally forming a silicon epitaxial liner on a surface of the fin-shaped structure;
forming a gap-fill insulating film on the silicon epitaxial liner to surround the fin-shaped structure;
applying an annealing process to the gap-fill insulating film;
repeating the forming of the gap-fill insulating film and the applying the annealing process at least once; and
partially removing the gap-fill insulating film to expose the fin-shaped structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jaemun
• Kim Dahye
• Kim Jinbum
• Kim Gyeom
• Kim Dohee
• Kim Dongwoo
• Lee Seunghun

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title

• H10D84/0158

  the components including FinFETs · CPC title