Dielectric isolation in gate-all-around devices

Patent metadata

Field	Value
Publication number	US-10636694-B2
Application number	US-201916562098-A
Country	US
Kind code	B2
Filing date	Sep 5, 2019
Priority date	Oct 9, 2017
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first layer deposited over a surface of a substrate;
a second set of layers of a channel material deposited over the first layer;
a liner deposited in a first recess;
a first connection end of a layer in the second set exposed from the liner;
an insulator material filling the first recess up to a height above the surface of the substrate; and
an electrical connection formed with a source/drain structure using the first connection end of the layer in the second set, wherein a remaining portion of the insulator below the height and a remaining portion of the liner in the first recess electrically isolates the source/drain structure from the substrate and increases impedance in a path of a substrate current from the source/drain structure to the substrate.

2. The semiconductor device of claim 1 , further comprising:
an epitaxy structure grown in electrical connection with the first connection end of the layer in the second set, wherein the epitaxy structure operates as the source/drain structure.

3. The semiconductor device of claim 1 , wherein the height above the substrate is zero.

4. The semiconductor device of claim 1 , wherein the height above the surface of the substrate reaches up to a substrate-facing surface of a bottom-most layer in the second set of layers.

5. The semiconductor device of claim 1 , wherein the first layer and the second set of layers together form a stack of layers, further comprising:
the first recess and a second recess formed by recessing the stack of layers, wherein the second recess exposes a second connection end of the layer in the second set, the second connection end being on an opposite side from the connection end, wherein the first recess and the second recess each reaches into the substrate for at least the fraction of the total depth of the substrate.

6. The semiconductor device of claim 1 , wherein a second layer immediately adjacent to the first layer comprises the second sacrificial material.

7. The semiconductor device of claim 1 , wherein a second layer immediately adjacent to the first layer comprises the channel material.

8. The semiconductor device of claim 1 , wherein the set of layers of the channel material includes a plurality of layers.

9. The semiconductor device of claim 1 , wherein the first layer comprises a first sacrificial material, wherein the first sacrificial material is etchable by a process at a first rate, wherein the second sacrificial material is etchable by the process at a second rate, and wherein the first rate is greater than the second rate.

10. A method comprising:
depositing, over a surface of a substrate, a first layer;
depositing, over the first layer, a second set of layers of a channel material;
depositing a liner in a first recess;
exposing from the liner a first connection end of a layer in the second set;
causing the first recess to be occupied with an insulator material up to a height above the surface of the substrate; and
enabling the first connection end of the layer in the second set to form an electrical connection with a source/drain structure, wherein a remaining portion of the insulator below the height and a remaining portion of the liner in the first recess electrically isolates the source/drain structure from the substrate and increases impedance in a path of a substrate current from the source/drain structure to the substrate.

11. The method of claim 10 , further comprising:
growing an epitaxy structure in electrical connection with the first connection end of the layer in the second set, wherein the epitaxy structure operates as the source/drain structure.

12. The method of claim 10 , wherein the height above the substrate is zero.

13. The method of claim 10 , wherein the height above the surface of the substrate reaches up to a substrate-facing surface of a bottom-most layer in the second set of layers.

14. The method of claim 10 , wherein the first layer and the second set of layers together form a stack of layers, further comprising:
recessing the stack of layers to form the first recess and a second recess, wherein the second recess exposes a second connection end of the layer in the second set, the second connection end being on an opposite side from the connection end, wherein the first recess and the second recess each reaches into the substrate for at least the fraction of the total depth of the substrate.

15. The method of claim 10 , wherein a second layer immediately adjacent to the first layer comprises the second sacrificial material.

16. The method of claim 10 , wherein a second layer immediately adjacent to the first layer comprises the channel material.

17. The method of claim 10 , wherein the set of layers of the channel material includes a plurality of layers.

18. The method of claim 10 , wherein the first layer comprises a first sacrificial material, wherein the first sacrificial material is etchable by a process at a first rate, wherein the second sacrificial material is etchable by the process at a second rate, and wherein the first rate is greater than the second rate.

19. A semiconductor fabrication system comprising a lithography component, the semiconductor fabrication system when operated on a wafer to fabricate a semiconductor device performing operations the comprising:
depositing, over a surface of a substrate, a first layer;
depositing, over the first layer, a second set of layers of a channel material;
depositing a liner in a first recess;
exposing from the liner a first connection end of a layer in the second set;
causing the first recess to be occupied with an insulator material up to a height above the surface of the substrate; and
enabling the first connection end of the layer in the second set to form an electrical connection with a source/drain structure, wherein a remaining portion of the insulator below the height and a remaining portion of the liner in the first recess electrically isolates the source/drain structure from the substrate and increases impedance in a path of a substrate current from the source/drain structure to the substrate.

20. The semiconductor fabrication system of claim 19 , further comprising:
growing an epitaxy structure in electrical connection with the first connection end of the layer in the second set, wherein the epitaxy structure operates as the source/drain structure.

Assignees

• IBM

Inventors

• Chao Robin Hsin Kuo
• Cheng Kangguo
• Loubet Nicolas
• Montanini Pietro
• Xie Ruilong

Classifications

• H01L29/42392

  Electricity · mapped topic

• H01L29/7853

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H01L29/40

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic