Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10164012-B2
Application number	US-201615064402-A
Country	US
Kind code	B2
Filing date	Mar 8, 2016
Priority date	Nov 30, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a first semiconductor layer sandwiched by second semiconductor layers in a first direction over a substrate;
patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers made by the second semiconductor layers and a channel layer made by the first semiconductor layer;
forming a sacrificial gate structure over the fin structure such that the sacrificial gate structure covers a part of the fin structure while remaining parts of the fin structure remains exposed;
removing the remaining parts of the fin structure, which are not covered by the sacrificial gate structure;
horizontally recessing the sacrificial layers so that edges of the sacrificial layers are located below a side face of the sacrificial gate structure;
forming a liner epitaxial layer at least on the recessed surface of the sacrificial layers;
forming a source/drain region;
removing the sacrificial gate structure;
removing the sacrificial layer in the fin structure after removing the sacrificial gate structure so that the channel layer is exposed; and
forming a gate dielectric layer and a gate electrode layer around the exposed channel layer.

2. The method of claim 1 , wherein the sacrificial layer in the fin structure and the first semiconductor layer in forming the source/drain region are removed by wet etching, respectively.

3. The method of claim 1 , wherein:
plural first semiconductor layers and plural second semiconductor layer are alternately formed over the substrate, and
in the fin structure, plural sacrificial layers and plural channel layers are alternately stacked.

4. The method of claim 1 , wherein:
the channel layer is made of Si or a Si-based compound.

5. The method of claim 4 , wherein:
the second semiconductor layer is made of SiGe.

6. The method of claim 1 , wherein:
in the forming the fin structure by patterning the first semiconductor layer and the second semiconductor layers, plural fin structures arranged in a horizontal direction parallel to a surface of the substrate are formed, and
in the forming the sacrificial gate structure, the sacrificial gate structure covers a part of each of the plural fin structures.

7. The method of claim 1 , wherein the liner epitaxial layer is undoped silicon.

8. The method of claim 1 , wherein a thickness of the liner epitaxial layer on the recessed surface of the channel layer is in a range from 1 nm to 4 nm.

9. The method of claim 1 , wherein, in the recessing the sacrificial layers, the channel layer is also horizontally recessed.

10. The method of claim 9 , wherein a recessed amount of the sacrificial layer is greater than a recessed amount of the channel layer.

11. The method of claim 9 , wherein the liner epitaxial layer is also formed on the recessed surface of the channel layer.

12. The method of claim 11 , wherein a thickness of the liner epitaxial layer on the recessed surface of the sacrificial layer is in a range from 5 nm to 10 nm.

13. The method of claim 11 , wherein a thickness of the liner epitaxial layer on the recessed surface of the channel layer is 20% to 60% of a thickness of the liner epitaxial layer on the recessed surface of the sacrificial layer.

14. The method of claim 11 , wherein the source/drain region is in contact with the liner epitaxial layer.

15. The method of claim 1 , wherein the liner epitaxial layer includes at least one of Si, SiP, and SiCP.

16. A method of manufacturing a semiconductor device, comprising:
forming a first semiconductor layer sandwiched by second semiconductor layers in a first direction over a substrate;
patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers made by the second semiconductor layers and a channel layer made by the first semiconductor layer;
forming a sacrificial gate structure over the fin structure such that the sacrificial gate structure covers a part of the fin structure while remaining parts of the fin structure remains exposed;
removing the remaining parts of the fin structure, which are not covered by the sacrificial gate structure;
forming a liner epitaxial layer at least on the recessed surface of the sacrificial layers;
forming a source/drain region;
removing the sacrificial gate structure;
removing the sacrificial layer in the fin structure after removing the sacrificial gate structure so that the channel layer is exposed; and
forming a gate dielectric layer and a gate electrode layer around the exposed channel layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fung Ka-Hing
• Ching Kuo-Cheng
• Leung Ying-Keung

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D64/01302

  the insulator being formed after the semiconductor body, the semiconductor being silicon · CPC title

• H01L29/785

  Electricity · mapped topic