Polyphase decimation FIR filters and methods

Patent metadata

Field	Value
Publication number	US-10050607-B2
Application number	US-201414573055-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 17, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

First claim

What is claimed is:

1. A polyphase decimation finite impulse response (FIR) filter apparatus comprising:
a sample integrator circuit configured to integrate input samples of the polyphaser FIR filter apparatus and to provide integrated input samples; and
a polyphase FIR filter circuit configured to process the integrated input samples and produce output samples with a decimation factor k, the polyphase FIR filter circuit comprising a plurality of multiplier accumulator circuits, each configured to accumulate products of FIR filter coefficients and respective integrated signal samples, wherein
each of the multiplier accumulator circuits receives a subset of the FIR filter coefficients, a controller selects a multiplier accumulator circuit from the plurality of multiplier accumulator circuits for producing a first output sample of the output samples of the polyphaser FIR filter circuit, and
the controller resets the selected multiplier accumulator circuit after the selected multiplier accumulator circuit produces the first output sample, wherein the FIR filter coefficients are derived as an nth difference of original filter coefficients, wherein n is a number of integrators in the sample integrator circuit.

2. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein the controller is configured to change the FIR filter coefficients supplied to the multiplier accumulator circuits, such that a decimation factor k is programmable in response to a control signal.

3. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein each of the multiplier accumulator circuits comprises at least one multiple constant multiplication circuit configured to provide products of an integrated input sample and two or more FIR filter coefficients, and an accumulator circuit configured to accumulate the products.

4. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein each of the multiplier accumulator circuits comprises a multiplier configured to receive integrated input samples at a first input and FIR filter coefficients from a coefficient memory at a second input, and an accumulator circuit configured to accumulate output values of the multiplier.

5. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein a number M of multiplier accumulator circuits is equal to a number of filter taps T of the FIR filter divided by the decimation factor k.

6. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein the FIR filter apparatus is configured to provide one output sample for every k input samples.

7. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein the controller is further configured to
change the subsets of FIR filter coefficients supplied to the multiplier accumulator circuits after every k cycles, and
select an output of a next one of the multiplier accumulator circuits after every k cycles.

8. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein the subsets of FIR filter coefficients received by each of the multiplier accumulator circuits rotate among the multiplier accumulator circuits in a cyclic manner.

9. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

10. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein each of the input samples have m bits, each of the integrated input samples have p bits, and p is greater than m.

11. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein the sample integrator circuit operates with two's complement arithmetic.

12. The polyphase decimation FIR filter apparatus as defined in claim 1 , wherein each of the multiplier accumulator circuits comprises a multiple constant multiplication (MCM) circuit configured to multiply the integrated input samples by the FIR filter coefficients using shift and add operations.

13. A polyphaser decimation FIR filter apparatus comprising:
a plurality of multiplier accumulator circuits configured to receive a plurality of integrated samples integrated in an integrator circuit comprising n integrators, the plurality of multiplier accumulator circuits comprising
a first multiplier accumulator circuit having
a first input configured to receive integrated input samples,
a second input configured to receive filter coefficients, and
an output configured to produce an output sample every k input cycles;

a second multiplier accumulator circuit having
a first input configured to receive integrated input samples
a second input configured to receive filter coefficients, and
an output configured to produce an output sample every k input cycles, wherein the filter coefficients are derived as an nth difference of original filter coefficients, wherein the original filter coefficients have a first word length, and wherein the filter coefficients have a second word length smaller than the first word length;

an output selector having
a first input configured to receive output samples from the first multiplier accumulator circuit,
a second input configured to receive output samples from the second multiplier accumulator circuit,
a select input configured to select a multiplier accumulator circuit from the plurality of multiplier accumulator circuits, and
an output configured to produce an output sample from the selected multiplier accumulator circuit every k cycles; and

a controller configured to
control the select input of the output selector to select a multiplier accumulator circuit, and
reset the selected multiplier accumulator circuit after the multiplier accumulator circuit is selected.

14. The polyphaser decimation FIR filter apparatus of claim 13 , wherein the controller is further configured to change the filter coefficients supplied to the plurality of multiplier accumulator circuits in a cyclic manner.

15. A method for polyphase decimation FIR filtering, comprising:
integrating input samples of a polyphase FIR filter circuit, by a sample integrator circuit, to provide integrated input samples; and
processing the integrated input samples, by the polyphase FIR filter circuit, to provide output samples, the processing comprising:
accumulating products of coefficients and the integrated input samples in respective multiplier accumulator circuits, wherein each of the respective multiplier accumulator circuits receives a subset of k coefficients, and wherein the coefficients are derived as an nth difference of original coefficients, wherein n is a number of integrators in the sample integrator circuit;
selecting an output of a selected multiplier accumulator circuit from the multiplier accumulator circuits after every k cycles, where k is a decimation factor; and
changing the subsets of k coefficients supplied to the respective multiplier accumulator circuits after every k cycles.

16. The method as defined in claim 15 , further comprising changing the subsets of k coefficients supplied to the multiplier accumulator circuits, such that the decimation factor k is programmable in response to a control signal.

17. The method as defined in claim 15 , wherein each of the multiplier accumulator circuits comprises at least one multiple constant multiplication circuit configured to provide products of an integrated input sample and two or more coefficients, and an accumulator circuit configured to accumulate the products.

18. The method as defined in claim 15 , wherei

Assignees

• St Microelectronics Int Nv

Inventors

• Bhargava Neha
• Bal Ankur

Classifications

• H03H17/0275

  comprising non-recursive filters · CPC title

• H03H2017/0245

  Measures to reduce power consumption · CPC title

• H03H17/0664 Primary

  where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation · CPC title