Integrated circuit with sequentially-coupled charge storage and associated techniques

Patent metadata

Field	Value
Publication number	US-12085442-B2
Application number	US-202117507585-A
Country	US
Kind code	B2
Filing date	Oct 21, 2021
Priority date	Oct 22, 2020
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

First claim

What is claimed is:

1. A method, comprising:
during a first time period, transferring first charge carriers from a first charge storage region to a second charge storage region; and
during a second time period:
receiving second charge carriers at the first charge storage region; and
reading out the first charge carriers from the second charge storage region.

2. The method of claim 1 , wherein:
the first and second charge carriers are generated in a photodetection region in response to arrival of photons at the photodetection region;
before the first time period, the first charge carriers are received at the first charge storage region from the photodetection region; and
during the second time period, the second charge carriers are received at the first charge storage region from the photodetection region.

3. The method of claim 2 , wherein:
over multiple sub-periods within the second time period, the second charge carriers are received at the first charge storage region; and
each sub-period within the second time period follows a respective excitation of a sample that causes the sample to emit the photons.

4. The method of claim 2 , wherein:
the second charge carriers are received at the first charge storage region from the photodetection region via a first charge transfer channel that connects the photodetection region to the first charge storage region; and
the first charge carriers are transferred from the first charge storage region to the second charge storage region via a second charge transfer channel that connects the first charge storage region to the second charge storage region.

5. The method of claim 2 , wherein:
the second charge carriers are received at the first charge storage region from the photodetection region via a first charge transfer channel that connects the photodetection region to the first charge storage region; and
the first charge carriers are transferred from the first charge storage region to the second charge storage region via:
a second charge transfer channel that connects the first charge storage region to an intermediate charge storage region;
the intermediate charge storage region; and
a third charge transfer channel that connects the intermediate charge storage region to the second charge storage region.

6. The method of claim 5 , wherein:
during a first sub-period of the second time period, the first charge carriers are read out from the second charge storage region to a readout region; and
during a second sub-period of the second time period, third charge carriers are read out from the intermediate charge storage region to the readout region via the second charge storage region.

7. The method of claim 1 , wherein reading out comprises transferring the first charge carriers from the second charge storage region to a readout region to be sampled.

8. A system, comprising:
a sample well configured to support a sample; and
an integrated circuit, comprising:
a photodetection region configured to generate charge carriers in response to receiving photons emitted by the sample;
a first charge storage region electrically coupled to the photodetection region to receive charge carriers; and
a second charge storage region electrically coupled to the first charge storage region to receive charge carriers,
wherein the integrated circuit is controllable to:
during a first time period, transfer first charge carriers from the first charge storage region to the second charge storage region; and
during a second time period:
read out the first charge carriers from the second charge storage region; and
receive second charge carriers at the first charge storage region from the photodetection region.

9. The system of claim 8 , wherein the integrated circuit is configured to induce a potential barrier between the first and second charge storage regions while the first charge storage region receives the second charge carriers from the photodetection region and the second charge storage region reads out the first charge carriers.

10. The system of claim 9 , wherein the integrated circuit further comprises a first transfer gate positioned, at least in part, between the first and second charge storage region and configured to receive a first control signal that causes the first transfer gate to control the potential barrier between the first and second charge storage regions while the first charge storage region receives the second charge carriers from the photodetection region and the second charge storage region reads out the first charge carriers.

11. The system of claim 10 , wherein the integrated circuit further comprises:
a first charge transfer channel connecting the first charge storage region to the second charge storage region and configured to be biased by the first transfer gate to control the potential barrier between the first and second charge storage regions.

12. The system of claim 11 , wherein the integrated circuit further comprises:
a drain region electrically coupled to the photodetection region to receive third charge carriers from the photodetection region;
a second transfer gate positioned, at least in part, between the photodetection region and the first charge storage region and configured to receive a second control signal that causes the second transfer gate to control a potential barrier between the photodetection region and the first charge storage region while the drain region receives the third charge carriers from the photodetection region; and
a second charge transfer channel connecting the photodetection region to the first charge storage region and configured to be biased by the second transfer gate to control the potential barrier between the photodetection region and the first charge storage region.

13. The system of claim 8 , wherein the integrated circuit further comprises:
an intermediate charge storage region electrically coupled between the first and second charge storage regions;
a first transfer gate positioned, at least in part, between the first and intermediate charge storage regions and configured to receive a first control signal that causes the first transfer gate to control a potential barrier between the first and intermediate charge storage regions while the first charge storage region receives the second charge carriers from the photodetection region and the intermediate and second charge storage regions read out the first charge carriers;
a first charge transfer channel connecting the first charge storage region to the intermediate charge storage region and configured to be biased by the first transfer gate to control the potential barrier between the first and intermediate charge storage regions;
a second transfer gate positioned, at least in part, between the intermediate and second charge storage regions and configured to receive a second control signal that causes the second transfer gate to control a potential barrier between the intermediate and second charge storage regions while the intermediate charge storage region receives the second charge carriers from the photodetection region via the first charge storage region and the second charge storage region reads out the first charge carriers; and
a second charge transfer channel connecting the intermediate charge storage region to the second charge storage region and configured to be biased by the second transfer gate to control the potential barrier between the intermediate and second charge storage regions.

14. The system of claim 8 , wherein the integrated circuit further comprises:
a readout region electrically coupled to the second charge storage region

Assignees

• Quantum Si Inc

Inventors

• Webster Eric A G
• Rearick Todd
• Thurston Thomas Raymond

Classifications

• H10F39/152

  One-dimensional array CCD image sensors · CPC title

• H10F39/1515

  Optical shielding · CPC title

• H10F39/011

  Manufacture or treatment of image sensors covered by group H10F39/12 · CPC title

• G01J2001/446

  Photodiode · CPC title

• B01J2219/00689

  using computers · CPC title