Display substrate, method of manufacturing the same, and display device including the same

Patent metadata

Field	Value
Publication number	US-12074175-B2
Application number	US-202217822751-A
Country	US
Kind code	B2
Filing date	Aug 26, 2022
Priority date	Oct 11, 2019
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

First claim

What is claimed is:

1. A method of manufacturing a display substrate, the method comprising:
forming a first gate electrode on a substrate;
forming a first gate insulating layer on the substrate to cover the first gate electrode;
forming an active layer on the first gate insulating layer, the active layer comprising a source region, a channel region, and a drain region;
forming a second gate insulating layer on the first gate insulating layer to cover the active layer;
forming a second gate electrode on the second gate insulating layer;
forming an interlayer insulating layer on the second gate insulating layer to cover the second gate electrode;
forming a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer to expose a top surface, a side wall, and a bottom surface of the active layer;
forming a second contact hole spaced from the active layer and through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer to expose the first gate electrode; and
forming a first electrode to fill the first contact hole and a second electrode to fill the second contact hole on the interlayer insulating layer,
wherein the first contact hole and the second contact hole are concurrently formed.

2. The method of claim 1 , wherein the first contact hole and the second contact hole are formed by a dry etching scheme utilizing one etching gas.

3. The method of claim 2 , wherein the first contact hole and the second contact hole are formed by the etching gas obtained by mixing a first gas comprising at least one of CHF 3 , C 4 F 8 , C 2 HF 5 , CH 2 F 2 , or CF 4 with a second gas comprising at least one of SF 6 or NF 3 .

4. The method of claim 1 , wherein the first contact hole and the second contact hole are formed by utilizing at least two different etching materials.

5. The method of claim 4 , wherein the forming of the first contact hole comprises:
forming a first portion of the first contact hole which exposes the top surface of the active layer by etching the second gate insulating layer;
forming a second portion of the first contact hole which exposes the side wall of the active layer by etching the active layer; and
forming a third portion of the first contact hole which exposes the bottom surface of the active layer by etching the portion of the first gate insulating layer, and
wherein a first etching material for forming the first portion is different from a second etching material for forming the second portion.

6. The method of claim 5 , wherein the first etching material comprises an etching gas obtained by mixing a first gas comprising at least one of CHF 3 , C 4 F 8 , C 2 HF 5 , CH 2 F 2 , or CF 4 with a second gas comprising at least one of SF 6 or NF 3 , or an etchant comprising a buffered oxide etchant (BOE).

7. The method of claim 5 , wherein the second etching material comprises an etching gas obtained by mixing a first gas comprising at least one of CHF 3 , C 4 F 8 , C 2 HF 5 , CH 2 F 2 , or CF 4 with a second gas comprising at least one of SF 6 or NF 3 .

8. The method of claim 5 , wherein a third etching material for forming the third portion is different from the second etching material.

9. The method of claim 8 , wherein the third etching material is the same as first etching material.

10. A method of manufacturing a display substrate, the method comprising:
forming a first electrode on a substrate;
forming a first insulating layer on the substrate to cover the first electrode;
forming an active layer on the first insulating layer, the active layer comprising a source region, a channel region, and a drain region;
forming a second insulating layer on the first insulating layer to cover the active layer;
forming a second electrode on the second insulating layer;
forming an interlayer insulating layer on the second insulating layer to cover the second electrode;
forming a first contact hole through the interlayer insulating layer, the second insulating layer, the active layer, and a portion of the first insulating layer to expose a top surface, a side wall, and a bottom surface of the active layer;
forming a second contact hole spaced from the active layer and through the interlayer insulating layer, the second insulating layer, and the first insulating layer to expose the first electrode; and
forming a third electrode in the first contact hole and a fourth electrode in the second contact hole,
wherein the first contact hole and the second contact hole are concurrently formed.

11. The method of claim 10 , wherein the first contact hole and the second contact hole are formed by a dry etching scheme utilizing one etching gas.

12. The method of claim 11 , wherein the first contact hole and the second contact hole are formed by the etching gas obtained by mixing a first gas comprising at least one of CHF 3 , C 4 F 8 , C 2 HF 5 , CH 2 F 2 , or CF 4 with a second gas comprising at least one of SF 6 or NF 3 .

13. The method of claim 10 , wherein the first contact hole and the second contact hole are formed by utilizing at least two different etching materials.

14. The method of claim 13 , wherein the forming of the first contact hole comprises:
forming a first portion of the first contact hole which exposes the top surface of the active layer by etching the second insulating layer;
forming a second portion of the first contact hole which exposes the side wall of the active layer by etching the active layer; and
forming a third portion of the first contact hole which exposes the bottom surface of the active layer by etching the portion of the first insulating layer, and
wherein a first etching material for forming the first portion is different from a second etching material for forming the second portion.

15. The method of claim 14 , wherein the first etching material comprises an etching gas obtained by mixing a first gas comprising at least one of CHF 3 , C 4 F 8 , C 2 HF 5 , CH 2 F 2 , or CF 4 with a second gas comprising at least one of SF 6 or NF 3 , or an etchant comprising a buffered oxide etchant (BOE).

16. The method of claim 14 , wherein the second etching material comprises an etching gas obtained by mixing a first gas comprising at least one of CHF 3 , C 4 F 8 , C 2 HF 5 , CH 2 F 2 , or CF 4 with a second gas comprising at least one of SF 6 or NF 3 .

17. The method of claim 14 , wherein a third etching material for forming the third portion is different from the second etching material.

18. The method of claim 17 , wherein the third etching material is the same as the first etching material.

Assignees

• Samsung Display Co Ltd

Inventors

• Cho Sungwon
• Jeong Yu-Gwang
• Choi Daewon
• Kim Seon-Il
• Bae Subin
• Yeo Yun Jong

Classifications

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D30/6743

  Silicon · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title