Array substrate, manufacturing method thereof and display device

Patent metadata

Field	Value
Publication number	US-9484465-B2
Application number	US-201314374987-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	May 30, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A array substrate is disclosed. The array substrate includes: a substrate ( 10 ); and a first gate metal layer ( 111 ), a first gate insulating layer ( 121 ), a semiconductor layer ( 13 ) and a source-drain electrode layer ( 14 ) disposed in this order on the substrate from bottom to top. The array substrate ( 10 ) further includes a second gate insulating layer ( 122 ) disposed on the source-drain electrode layer ( 14 ); and a second gate metal layer ( 112 ) disposed on the second gate insulating layer ( 122 ). A method of manufacturing an array substrate is also disclosed.

First claim

The invention claimed is:

1. An array substrate, comprising: a substrate; and a first gate metal layer, a first gate insulating layer, a semiconductor layer and a source-drain electrode layer disposed in this order on the substrate from bottom to top; the array substrate further comprising:
a second gate insulating layer disposed on the source-drain electrode layer;
a second gate metal layer disposed on the second gate insulating layer;
a first common electrode line disposed in a same layer as the first gate metal layer or disposed in a same layer as the second gate metal layer; and
a second common electrode line, wherein:
in condition that the first common electrode line and the first gate metal layer are in same and one layer, the second common electrode line and the second gate metal layer are in same and one layer; and
in condition that the first common electrode line and the second gate metal layer are in same and one layer, the second common electrode line and the first gate metal layer are in same and one layer.

2. The array substrate of claim 1 , wherein the second common electrode line is connected in parallel with the first common electrode line, and a line width of the second common electrode line is same as that of the first common electrode line.

3. The array substrate of claim 1 , further comprising:
a resin layer overlaying the second gate metal layer; and
a first electrode and a second electrode configured for generating an electric field therebetween to drive liquid crystals, and a passivation layer disposed between the first electrode and the second electrode, the first electrode being disposed on the resin layer and the second electrode being disposed on the passivation layer.

4. The array substrate of claim 3 , wherein the first electrode is connected with the first common electrode line through a via in the resin layer.

5. The array substrate of claim 3 , wherein the second electrode is connected with a drain of the source-drain electrode layer through drain vias respectively in the passivation layer, the resin layer and the second gate insulating layer.

6. The array substrate of claim 5 , wherein the second gate metal layer is located directly over the first gate metal layer.

7. A display device, comprising the array substrate of claim 1 .

8. A method of manufacturing an array substrate, comprising:
forming a first gate metal layer on a substrate;
forming a first gate insulating layer on the substrate formed with the first gate metal layer;
forming a semiconductor layer, a source-drain electrode layer, a second gate insulating layer and a second gate metal layer on the substrate in this order and from bottom to top, the substrate being formed with the first gate metal layer and the first gate insulating layer; and
forming a first common electrode line at the same time as forming the second gate metal layer.

9. The method of claim 8 , further comprising:
forming a resin layer and a pattern of a resin layer via on the substrate formed with the first gate metal layer, the first gate insulating layer, the semiconductor layer, the source-drain electrode layer, the second gate insulating layer and the second gate metal layer;
forming a first transparent conductive film layer on the substrate with completion of previous step and forming a first electrode by patterning process;
forming a passivation layer and a pattern of passivation layer via;
forming a second transparent conductive film layer and forming a second electrode by patterning process.

10. The method of claim 8 , further comprising: forming a second common electrode line at the same time as forming the first gate metal layer.

11. The method of claim 10 , wherein the second common electrode line are connected in parallel with the first common electrode line, and a line width of the second common electrode line is same as that of the first common electrode line.

12. The method of claim 9 , wherein the first gate metal layer and the second gate metal layer are formed by patterning process using same and one mask.

13. The method of claim 8 , wherein the first gate metal layer and the second gate metal layer are formed by patterning process using same and one mask.

14. An array substrate, comprising: a substrate; and a first gate metal layer, a first gate insulating layer, a semiconductor layer and a source-drain electrode layer disposed in this order on the substrate from bottom to top; the array substrate further comprising:
a second gate insulating layer disposed on the source-drain electrode layer;
a second gate metal layer disposed on the second gate insulating layer; and
a first common electrode line disposed in a same layer as one of the first gate metal layer and the second gate metal layer;
a resin layer overlaying the second gate metal layer; and
a first electrode and a second electrode configured for generating an electric field therebetween to drive liquid crystals, and a passivation layer disposed between the first electrode and the second electrode, the first electrode being disposed on the resin layer and the second electrode being disposed on the passivation layer,
wherein the first electrode is connected with the first common electrode line through a via in the resin layer.

15. The array substrate of claim 14 , further comprising: a second common electrode line, wherein:
in condition that the first common electrode line and the first gate metal layer are in same and one layer, the second common electrode line and the second gate metal layer are in same and one layer; and
in condition that the first common electrode line and the second gate metal layer are in same and one layer, the second common electrode line and the first gate metal layer are in same and one layer.

16. The array substrate of claim 15 , wherein the second common electrode line is connected in parallel with the first common electrode line, and a line width of the second common electrode line is same as that of the first common electrode line.

17. The array substrate of claim 14 , wherein the second electrode is connected with a drain of the source-drain electrode layer through drain vias respectively in the passivation layer, the resin layer and the second gate insulating layer.

18. The array substrate of claim 14 , wherein the second gate metal layer is located directly over the first gate metal layer.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Choi Hyun Sic
• Li Hui
• Xu Zhiqiang
• Um Yoon Sung

Classifications

• H10D30/6734 Primary

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• G02F1/134363 Primary

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title