Thin film transistor substrate and display apparatus using the same

Patent metadata

Field	Value
Publication number	US-9842864-B2
Application number	US-201514871070-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2014
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A thin film transistor (TFT) substrate is disclosed. The TFT substrate includes a substrate, a blocking layer, a source electrode, and a drain electrode on a same layer over the substrate, an active layer overlapping the blocking layer, the source electrode, and the drain electrode, a gate insulation layer over the active layer, a first gate electrode over the gate insulation layer, an interlayer dielectric over the first gate electrode, a first connection electrode over the interlayer dielectric and connected to the active layer and the source electrode through a first contact hole, a second connection electrode over the interlayer dielectric and connected to the active layer and the drain electrode through a second contact hole, a planarization layer over the first connection electrode and the second connection electrode, and a pixel electrode over the planarization layer and connected to the second connection electrode through a third contact hole.

First claim

What is claimed is:

1. A thin film transistor substrate comprising:
a substrate;
a blocking layer, a source electrode, and a drain electrode disposed on a same layer over the substrate;
an active layer disposed to overlap the blocking layer, the source electrode, and the drain electrode;
a gate insulation layer disposed over the active layer;
a first gate electrode disposed over the gate insulation layer;
an interlayer dielectric disposed over the first gate electrode;
a first connection electrode disposed over the interlayer dielectric and connected to the active layer and the source electrode through a first contact hole;
a second connection electrode disposed over the interlayer dielectric and connected to the active layer and the drain electrode through a second contact hole;
a planarization layer disposed over the first connection electrode and the second connection electrode; and
a pixel electrode disposed over the planarization layer and connected to the second connection electrode through a third contact hole.

2. The thin film transistor substrate of claim 1 , further comprising:
a thin film transistor area and a capacitor area; and
at least one capacitor formed in the capacitor area,
wherein the blocking layer, the source electrode, and the drain electrode are formed in the thin film transistor area.

3. The thin film transistor substrate of claim 1 , further comprising:
a first buffer layer disposed over the substrate; and
a second buffer layer disposed over the first buffer layer,
wherein the source electrode and the drain electrode are interposed between the first buffer layer and the second buffer layer.

4. The thin film transistor substrate of claim 1 ,
wherein the source electrode and the drain electrode are formed of a material which differs from the material of the blocking layer.

5. The thin film transistor substrate of claim 2 ,
wherein the at least one capacitor comprises a first capacitor electrode and a second capacitor electrode, and
wherein the second capacitor electrode and the first gate electrode are formed on a same layer.

6. The thin film transistor substrate of claim 5 ,
wherein the second capacitor electrode and the first gate electrode are formed of a same material.

7. The thin film transistor substrate of claim 5 ,
wherein the first capacitor electrode and the second capacitor electrode laterally overlap each other.

8. The thin film transistor substrate of claim 1 , further comprising:
a second gate electrode;
wherein the second gate electrode, the first connection electrode, and the second connection electrode are formed on a same layer, and
wherein the second gate electrode, the first connection electrode, and the second connection electrode are formed on the interlayer dielectric.

9. The thin film transistor substrate of claim 1 ,
wherein the first connection electrode and the second connection electrode each extend through the interlayer dielectric, the gate insulation layer, and the active layer and electrically connect to the source electrode and the drain electrode, respectively.

10. The thin film transistor substrate of claim 1 ,
wherein the first contact hole and the second contact hole each are in direct contact with the active layer.

11. The thin film transistor substrate of claim 1 ,
wherein the active layer comprises a first region having two first partial regions, the first partial regions having a first doping concentration, a second region having two second partial regions, the second partial regions having a second doping concentration being smaller than the first doping concentration, and a channel region,
wherein one second partial region is arranged adjacent to the channel region on one side of the channel region, and another second partial region is arranged adjacent to the channel region on an opposite side of the channel region,
wherein one first partial region is arranged adjacent to one second partial region on one side, and another first partial region is arranged adjacent to the other second partial region,
wherein the first connection electrode is electrically coupled with the one first partial region and with the source electrode, and
wherein the second connection electrode is electrically coupled with the other first partial region and with the drain electrode.

12. The thin film transistor substrate of claim 11 ,
wherein one first partial region laterally overlaps the source electrode, wherein the other first partial region laterally overlaps the drain electrode, and
wherein the channel region laterally overlaps the blocking layer.

13. A display apparatus, comprising:
a thin film transistor substrate; and
a further substrate arranged opposite the thin film transistor substrate,
wherein the thin film transistor substrate comprises:
a substrate;
a blocking layer, a source electrode, and a drain electrode disposed on a same layer over the substrate;
an active layer disposed to overlap the blocking layer, the source electrode, and the drain electrode;
a gate insulation layer disposed over the active layer;
a first gate electrode disposed over the gate insulation layer;
an interlayer dielectric disposed over the first gate electrode;
a first connection electrode disposed over the interlayer dielectric and connected to the active layer and the source electrode through a first contact hole;
a second connection electrode disposed over the interlayer dielectric and connected to the active layer and the drain electrode through a second contact hole;
a planarization layer disposed over the first connection electrode and the second connection electrode; and
a pixel electrode disposed over the planarization layer and connected to the second connection electrode through a third contact hole.

14. The display apparatus of claim 13 , further comprising:
a liquid crystal layer formed between the thin film transistor substrate and the further substrate.

15. A display apparatus, comprising:
a thin film transistor substrate; and
an organic layer structure configured to emit light,
wherein the organic layer structure is disposed over a pixel electrode and
wherein the thin film transistor substrate comprises:
a substrate;
a blocking layer, a source electrode, and a drain electrode disposed on a same layer over the substrate;
an active layer disposed to overlap the blocking layer, the source electrode, and the drain electrode;
a gate insulation layer disposed over the active layer;
a first gate electrode disposed over the gate insulation layer;
an interlayer dielectric disposed over the first gate electrode;
a first connection electrode disposed over the interlayer dielectric and connected to the active layer and the source electrode through a first contact hole;
a second connection electrode disposed over the interlayer dielectric and connected to the active layer and the drain electrode through a second contact hole;
a planarization layer disposed over the first connection electrode and the second connection electrode; and
a pixel electrode disposed over the planarization layer and connected to the second connection electrode through a third contact hole.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Hyun Ho
• Kim Woo Joon

Classifications

• H01L27/3272

  Electricity · mapped topic

• H01L27/3248

  Electricity · mapped topic

• H01L27/1255 Primary

  Electricity · mapped topic

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• H01L29/78645

  Electricity · mapped topic