Metal-free frame design for silicon bridges for semiconductor packages

Patent metadata

Field	Value
Publication number	US-11626372-B2
Application number	US-202117143142-A
Country	US
Kind code	B2
Filing date	Jan 6, 2021
Priority date	Oct 29, 2015
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate having an insulating layer thereon, the substrate having a perimeter, and the substrate comprising silicon;
a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;
a first metal ring in the dielectric material stack and continuous around the conductive routing;
a second metal ring in the dielectric material stack and continuous around the first metal ring, wherein at least one of the first metal ring or the second metal ring comprises a vertical stack of alternating metal lines and vias, the alternating metal lines comprising a first metal line, a second metal line above the first metal line, a third metal line above the second metal line, and a fourth metal line above the third metal line;
a plurality of staggered non-continuous metal rings between the first metal ring and the second metal ring; and
a metal-free region of the dielectric material stack surrounding the second metal ring, the metal-free region adjacent to the second metal ring and adjacent to the perimeter of the substrate.

2. The semiconductor structure of claim 1 , wherein at least one of the first metal ring or the second metal ring provides a hermetic seal for the metallization structure.

3. The semiconductor structure of claim 1 , further comprising:
a metal feature between the first metal ring and the second metal ring, the metal feature selected from the group consisting of an alignment mark, a dummy feature, and a test feature.

4. The semiconductor structure of claim 1 , wherein an uppermost layer of the metallization structure comprises first and second pluralities of conductive pads thereon.

5. The semiconductor structure of claim 4 , wherein the conductive routing electrically couples the first plurality of conductive pads with the second plurality of conductive pads.

6. The semiconductor structure of claim 4 , wherein the first and second pluralities of conductive pads comprise a layer of copper having a thickness of greater than approximately 5 microns.

7. The semiconductor structure of claim 1 , wherein the substrate is free from having semiconductor devices therein.

8. The semiconductor structure of claim 1 , wherein the substrate is a single crystalline silicon substrate.

9. The semiconductor structure of claim 1 , further comprising:
a crack in the metal-free region of the dielectric material stack, the crack propagating through the second metal ring but not through the first metal ring.

10. A semiconductor package, comprising:
an embedded interconnection bridge comprising a bridge within a semiconductor package substrate, the bridge comprising:
a substrate having an insulating layer thereon, the substrate having a perimeter, and the substrate comprising silicon;
a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;
a first metal ring in the dielectric material stack and continuous around the conductive routing;
a second metal ring in the dielectric material stack and continuous around the first metal ring, wherein at least one of the first metal ring or the second metal ring of the bridge comprises a vertical stack of alternating metal lines and vias, the alternating metal lines comprising a first metal line, a second metal line above the first metal line, a third metal line above the second metal line, and a fourth metal line above the third metal line;
a plurality of staggered non-continuous metal rings between the first metal ring and the second metal ring; and
a metal-free region of the dielectric material stack surrounding the second metal ring, the metal-free region adjacent to the second metal ring and adjacent to the perimeter of the substrate;

a first semiconductor die on the semiconductor package substrate; and
a second semiconductor die on the semiconductor package substrate and adjacent the first semiconductor die, the second semiconductor die electrically coupled to the first semiconductor die by the conductive routing of the metallization structure of the bridge.

11. The semiconductor package of claim 10 , wherein the first semiconductor die is a memory die, and the second semiconductor die is a logic die.

12. The semiconductor package of claim 10 , wherein at least one of the first metal ring or the second metal ring of the bridge provides a hermetic seal for the metallization structure of the bridge.

13. The semiconductor package of claim 10 , the bridge further comprising:
a metal feature between the first metal ring and the second metal ring, the metal feature selected from the group consisting of an alignment mark, a dummy feature, and a test feature.

14. The semiconductor package of claim 10 , wherein an uppermost layer of the metallization structure of the bridge comprises first and second pluralities of conductive pads thereon, wherein the first semiconductor die is attached to the first plurality of conductive pads, and wherein the second semiconductor die is attached to the second plurality of conductive pads.

15. The semiconductor package of claim 14 , wherein the conductive routing of the bridge electrically couples the first plurality of conductive pads to the second plurality of conductive pads.

16. The semiconductor package of claim 14 , wherein the first and second pluralities of conductive pads of the bridge comprise a layer of copper having a thickness of greater than approximately 5 microns.

17. The semiconductor package of claim 10 , wherein the substrate is free from having semiconductor devices therein.

18. The semiconductor package of claim 10 , the bridge further comprising:
a crack in the metal-free region of the dielectric material stack of the bridge, the crack propagating through the second metal ring but not through the first metal ring of the bridge.

Assignees

• Intel Corp

Inventors

• Kim Dae-Woo
• Sharan Sujit
• Agraharam Sairam

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title