Method for forming interconnect structure

Patent metadata

Field	Value
Publication number	US-9966304-B2
Application number	US-201615263249-A
Country	US
Kind code	B2
Filing date	Sep 12, 2016
Priority date	Jun 27, 2013
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an α-phase inducing metal layer is introduced on a first Ta barrier layer of β phase to induce the subsequent deposition of Ta thereon into the formation of an α-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of α phase has a lower Rc than that of the β-phase Ta barrier layer.

First claim

What is claimed is:

1. A method for forming an interconnect structure, the method comprising:
depositing a dielectric layer on a substrate;
forming an opening in the dielectric layer; and
forming a conductive feature, comprising:
depositing a first Ta barrier layer in the opening;
forming an alpha (α)-phase inducing metal layer on the first Ta barrier layer such that the α-phase inducing metal layer covers only a bottom surface of the first Ta barrier layer;
forming a second Ta barrier layer on the α-phase inducing metal layer;
forming a seed layer on the second Ta barrier layer; and
filling the opening with a conductive layer.

2. The method of claim 1 , wherein at least one of the depositing of the first Ta barrier layer and the forming of the second Ta barrier layer is performed by a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

3. The method of claim 1 , wherein the forming of the seed layer includes a PVD process, a CVD process, an ALD process, an electroplating, an electroless plating, or a combination thereof.

4. The method of claim 1 , wherein the filling of the opening with the conductive layer includes electroplating or electroless plating a metal selected from the group consisting of copper (Cu), copper magnesium (CuMg), copper aluminum (CuAl), copper manganese (CuMn), copper titanium (CuTi), copper silicon (CuSi), copper tungsten (CuW), copper tantalum (CuTa), copper zirconium (CuZr), copper molybdenum (CuMo), and combinations thereof.

5. The method of claim 1 , further comprising repeating the forming of the conductive feature to form a second conductive feature overlying the conductive layer.

6. The method of claim 1 , wherein the forming of the α-phase inducing metal layer includes electroplating a metal layer selected from the group consisting of Cu, Cobalt (Co), Titanium (Ti), and Ruthenium (Ru).

7. The method of claim 1 , wherein the forming of the α-phase inducing metal layer includes electroless-plating a metal layer selected from the group consisting of Cu, Co, Ti, and Ru.

8. The method of claim 1 , further comprising partially removing the conductive layer and the seed layer to expose the first or second Ta barrier layer.

9. The method of claim 8 , wherein the partially removing of the conductive layer and the seed layer comprises a chemical-mechanical polishing (CMP) process or an electropolishing process.

10. The method of claim 1 , wherein the first Ta barrier layer has a resistivity higher than that of the second Ta barrier layer.

11. The method of claim 1 , wherein the seed layer is different from the conductive layer in composition.

12. A method of forming a conductive feature in a semiconductor structure, the method comprising:
forming a beta (β)-phase Ta barrier layer in an opening in a dielectric layer on a semiconductor substrate;
depositing an alpha (α)-phase inducing metal layer only on a bottom surface of the beta (β)-phase Ta barrier layer;
growing an alpha (α)-phase Ta barrier layer on the alpha (α)-phase inducing metal layer;
forming a seed layer over the alpha (α)-phase Ta barrier layer; and
filling the opening with a conductive layer.

13. The method of claim 12 , wherein the seed layer is different from the conductive layer in composition.

14. The method of claim 12 , further comprising forming a second conductive feature overlying or underlying the conductive feature.

15. The method of claim 12 , wherein the beta (β)-phase Ta barrier layer has a resistivity higher than that of the alpha (α)-phase Ta barrier layer.

16. A method of forming a semiconductor structure, the method comprising:
forming an opening in a dielectric layer;
depositing a beta (β)-phase Ta barrier layer in the opening;
depositing an alpha (α)-phase inducing metal layer over the beta (β)-phase Ta barrier layer such that the alpha (α)-phase inducing metal layer is formed only over a bottom surface of the beta (β)-phase Ta barrier layer;
depositing an alpha (α)-phase Ta barrier layer over the alpha (α)-phase inducing metal layer; and
depositing a seed layer on the alpha (α)-phase Ta barrier layer; and
filling the opening with a conductive layer.

17. The method of claim 16 , wherein the alpha (α)-phase Ta barrier layer is deposited to a thickness in a range of 5 to 60 angstroms.

18. The method of claim 16 , wherein the beta (β)-phase Ta barrier layer is deposited to a thickness in a range of 10 to 100 angstroms.

19. The method claim 16 , wherein the alpha (α)-phase inducing metal layer is deposited to a thickness in a range of 15 to 50 angstroms.

20. The method of claim 16 , wherein the beta (β)-phase Ta barrier layer has a resistivity higher than that of the alpha (α)-phase Ta barrier layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Yu-Hung
• Yeh Ching-Fu
• Tsai Hsin-Chen
• Liang Yao-Hsiang
• Chang Yu-Min
• Lin Shih-Chi

Classifications

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/4424

  Copper alloys · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/045

  for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD] · CPC title