Three dimensional perpendicular magnetic tunnel junction with thin film transistor array

Patent metadata

Field	Value
Publication number	US-12069964-B2
Application number	US-202217811581-A
Country	US
Kind code	B2
Filing date	Jul 9, 2022
Priority date	May 18, 2018
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region in each cavity region between adjacent 3D structures over the substrate, and forming a first gate region over the first isolation region in each cavity region.

First claim

What is claimed is:

1. A method for manufacturing a magnetic random access memory array, the method comprising:
forming a source region within a surface of a substrate;
forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region;
depositing a channel material on a surface of at least one sidewall of each 3D structure;
depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of each 3D structure;
forming a first isolation region in each cavity region between adjacent 3D structures over the substrate; and
forming a first gate region over the first isolation region in each cavity region.

2. The method of claim 1 , further comprising:
forming a second isolation region over the first gate region in each cavity region.

3. The method of claim 2 , further comprising:
alternately forming an n th gate region and an (n+1) th isolation region in each cavity region until reaching a top of the array of 3D structures, wherein n is integral larger than 1.

4. The method of claim 3 , wherein each 3D structure comprises a first buffer layer over the substrate and a dielectric layer over the first buffer layer.

5. The method of claim 4 , wherein each 3D structure further comprises a plurality of buffer layers and a plurality of magnetoresistive tunnel junction (MTJ) elements disposed over the dielectric layer.

6. The method of claim 5 , wherein the plurality of MTJ elements are deposited alternately with the plurality of buffer layers.

7. The method of claim 5 , wherein a k th gate region has a thickness equivalent to or greater than a corresponding (k−1) th MTJ element formed in the respective 3D structure.

8. The method of claim 3 , wherein each isolation region comprises a sacrificial semiconductor material.

9. The method of claim 8 , further comprising:
removing the sacrificial semiconductor material of each isolation region.

10. The method of claim 9 , further comprising:
forming a functional isolation region in a space formed by removing the sacrificial semiconductor material of each isolation region.

11. The method of claim 1 , wherein forming the source region within the surface of the substrate further comprises:
forming portions of silicon dioxide between different portions of the source region.

12. The method of claim 11 , wherein forming the source region within the surface of the substrate further comprises:
recessing the portions of the silicon dioxide;
depositing amorphous or poly-phase silicon above the recessed portions of the silicon dioxide and a surface of the source region; and
planarizing the substrate following the deposition of the amorphous or poly-phase silicon.

13. The method of claim 12 , further comprising:
annealing the surface of the substrate.

14. The method of claim 13 , wherein the surface of the substrate is annealed by using a laser annealing technique to form single-crystalline silicon above the portions of amorphous or poly-phase silicon and the source region.

Assignees

• Integrated Silicon Solution Cayman Inc

Inventors

• Kim Kuk-Hwan
• Beery Dafna
• Levi Amitay
• Walker Andrew J

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title