Three dimensional perpendicular magnetic tunnel junction with thin film transistor array

Patent metadata

Field	Value
Publication number	US-11417829-B2
Application number	US-201815984133-A
Country	US
Kind code	B2
Filing date	May 18, 2018
Priority date	May 18, 2018
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.

First claim

What is claimed is:

1. A magnetic random access memory array, comprising: a substrate having a sourceline formed therein;
a pillar structure between the sourceline on one side and a bitline on an opposite second side in a vertical direction, the pillar structure comprising a plurality of homogeneous magnetic memory elements stacked over one another along the vertical direction, each magnetic memory element comprising a magnetic reference layer, a magnetic free layer, and a non-magnetic, electrically-insulating magnetic barrier layer positioned between the reference layer and the free layer; and
a transistor located between the sourceline and the pillar structure, the transistor being functional to selectively electrically connect the pillar structure with the sourceline;
wherein the transistor further comprises:
a column of epitaxial semiconductor material having an outer side, the column of epitaxial semiconductor material forming a channel of the transistor structure;
a gate dielectric surrounding the column of epitaxial semiconductor material and contacting the side of the column of epitaxial semiconductor material; and
an electrically conductive gate structure surrounding the gate dielectric and the column of epitaxial semiconductor material such that the gate dielectric separates the electrically conductive gate structure from the column of epitaxial semiconductor material,
wherein the gate structure comprises a plurality of gate regions separated from one another along the vertical direction, each of the plurality of gate regions surrounding a sidewall of a corresponding one of the plurality of homogeneous magnetic memory elements in a horizontal direction.

2. The magnetic random access memory array as in claim 1 , wherein the pillar structure further comprises at least one buffer layer separating the plurality of homogeneous magnetic memory elements from one another.

3. The magnetic random access memory array as in claim 1 , wherein the column of epitaxial semiconductor material comprises Si.

4. The magnetic random access memory array as in claim 1 , wherein the electrically conductive gate structure comprises one or more of W, TiNi, TaN, TiN, and Ti.

5. The magnetic random access memory array as in claim 1 , wherein the electrically conductive gate structure comprises one or more of W, TiNi, TaN, TiN, and Ti and the gate dielectric comprises one or more of SiO2, HfO2, Al2O3and ZrO2.

6. The magnetic random access memory array as in claim 1 , wherein the sourceline comprises an n+ doped region formed in the substrate.

7. The magnetic random access memory array as in claim 6 , wherein the substrate comprises a semiconductor material.

8. The magnetic random access memory array as in claim 1 , wherein the substrate comprises Si and the sourceline comprises an n+ doped region formed in the Si.

9. The magnetic random access memory array as in claim 2 , wherein the at least one buffer layer comprises one or more of Ni, Au, Pt, or Al.

10. A magnetic random access memory array comprising:
a substrate;
a sourceline formed on the substrate;
a plurality of pillar structures formed over the substrate, each of the pillar structures being disposed between the sourceline on one side and a bitline on an opposite second side in a vertical direction and comprising a plurality of homogeneous magnetic memory elements stacked over one another along the vertical direction, each of the magnetic memory elements comprising a magnetic reference layer, a magnetic free layer, and a non-magnetic, electrically-insulating magnetic barrier layer positioned between the reference layer and the free layer; and
a plurality of transistors each transistor being located between the sourceline and one of the plurality of pillar structures, the transistor being functional to selectively electrically connect the pillar structure with the sourceline;
wherein the transistors each further comprise:
a column of epitaxial semiconductor material forming a channel of the transistor, the column of epitaxial semiconductor having an outer side;
a gate dielectric surrounding the column of epitaxial semiconductor material and contacting the side of the column of epitaxial semiconductor material; and
an electrically conductive gate structure surrounding the gate dielectric and the column of epitaxial semiconductor material such that the gate dielectric separates the annular electrically conductive gate structure from the column of epitaxial semiconductor material,
wherein the gate structure comprises a plurality of gate regions separated from one another along the vertical direction, each of the plurality of gate regions surrounding a sidewall of a corresponding one of the plurality of homogeneous magnetic memory elements in a horizontal direction.

11. The magnetic random access memory array as in claim 10 , wherein each of the plurality of pillar structures further comprises at least one buffer layer separating the plurality of homogeneous magnetic memory elements.

12. The magnetic random access memory array as in claim 10 , wherein the column of epitaxial semiconductor material comprises Si.

13. The magnetic random access memory array as in claim 10 , wherein the electrically conductive gate structure comprises one or more of W, TiNi, TaN, TiN, and Ti.

14. The magnetic random access memory array as in claim 10 , wherein:
the column of epitaxial semiconductor material comprises Si;
the electrically conductive gate structure comprises one or more of W, TiNi, TaN, TiN, and Ti; and
the gate dielectric comprises one or more of SiO2, HfO2, Al2O3and ZrO2.

Assignees

• Integrated Silicon Solution Cayman Inc

Inventors

• Kim Kuk-Hwan
• Beery Dafna
• Levi Amitay
• Walker Andrew J

Classifications

• G11C11/1659 Primary

  Cell access · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G01R33/098

  comprising tunnel junctions, e.g. tunnel magnetoresistance sensors · CPC title

• H01L43/02 Primary

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic