Spin torque transfer mram device formed on silicon stud grown by selective epitaxy

Patent metadata

Field	Value
Publication number	US-2016248003-A1
Application number	US-201514749179-A
Country	US
Kind code	A1
Filing date	Jun 24, 2015
Priority date	Feb 20, 2015
Publication date	Aug 25, 2016
Grant date	—

Abstract

A technique relates magnetoresistive random access memory (MRAM). A dielectric layer is disposed on a transistor, and the transistor is formed in a uniform crystalline substrate. A hole is formed through the dielectric layer to reach the transistor. A polycrystalline material is disposed in the hole by using selective epitaxial growth (SEG), and the polycrystalline material is annealed to create an epitaxial stud. A magnetic tunnel junction (MTJ) is disposed on the epitaxial stud (SEG).

First claim

1 . A method of forming a magnetoresistive random access memory (MRAM) device, the method comprising:
disposing a dielectric layer on a transistor, wherein the transistor is formed in a uniform crystalline substrate; forming a hole through the dielectric layer to reach the transistor; disposing a polycrystalline material in the hole by using selective epitaxial growth (SEG), wherein the polycrystalline material is annealed to create an epitaxial stud; and disposing a magnetic tunnel junction (MTJ) on the epitaxial stud, wherein the magnetic tunnel junction is grown to have the lattice match to both the epitaxial stud and the uniform crystalline substrate.

2 . The method of claim 1 , wherein the transistor comprises a source and a drain;
wherein the hole is over the source or the drain of the transistor.

3 . The method of claim 2 , wherein the epitaxial stud is disposed over the source or the drain of the transistor.

4 . The method of claim 2 , wherein the magnetic tunnel junction is disposed over the source or the drain of the transistor.

5 . The method of claim 1 , wherein the magnetic tunnel junction comprises a tunnel barrier layer sandwiched between a free magnetic layer and a reference magnetic layer.

6 . The method of claim 5 , wherein an interface layer is disposed between the magnetic tunnel junction and the epitaxial stud.

7 . The method of claim 1 , wherein the epitaxial stud is doped with dopants such that electrical current is allowed to flow between the transistor and the magnetic tunnel junction.

8 . The method of claim 1 , wherein annealing polycrystalline material to create the epitaxial stud forms a lattice match to the uniform crystalline substrate.

9 . (canceled)

Assignees

• IBM

Inventors

• Debrosse John K
• Nowak Janusz J

Classifications

• H01L27/228

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title