Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-12068255-B2
Application number	US-202117399283-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Aug 11, 2021
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, the memory-block regions comprising part of a memory-plane region, the lower portion comprising a lowest of the first tiers that comprises sacrificial material;
forming a wall in the lowest first tier aside the sacrificial material, the wall being of different composition from that of the sacrificial material and being horizontally-elongated, the wall being one of (a) or (b), where:
(a): in the memory-plane region longitudinally-along one of the memory-block regions, the one memory-block region being immediately-adjacent a through-array-via (TAV) region that is in the memory-plane region, the wall being along an edge of the one memory-block region that is closest to the TAV region that is in the memory-plane region; and
(b): in a region that is edge-of-plane relative to the memory-plane region, the edge-of-plane region comprising a TAV region, the wall being horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region;

after forming the wall, forming the vertically-alternating different-composition first tiers and second tiers of an upper portion of the stack above the lower portion, and forming channel-material strings that extend through the first tiers and the second tiers in the upper portion to the lower portion;
forming horizontally-elongated trenches through the upper portion and that are individually between immediately-laterally-adjacent of the memory-block regions; and
through the horizontally-elongated trenches, isotropically etching the sacrificial material selectively relative to the wall and replacing the sacrificial material with conducting material that directly electrically couples together channel material of the channel-material strings and the conductor material of the conductor tier.

2. The method of claim 1 comprising the (a).

3. The method of claim 2 wherein the wall is along all of the edge of the one memory-block region that is closest to the TAV region that is in the memory-plane region.

4. The method of claim 1 comprising the (b).

5. The method of claim 4 wherein the wall is along all of the edge of the TAV region that is in the edge-of-plane region.

6. The method of claim 1 comprising another of said wall in the other of the (a) or the (b).

7. The method of claim 1 wherein the wall is insulative.

8. The method of claim 1 wherein the memory-block regions are elongated horizontally-parallel relative one another, the wall being horizontally-elongated parallel the memory-block regions.

9. The method of claim 1 wherein the wall is directly against the sacrificial material.

10. The method of claim 9 wherein the wall and sacrificial material have the same thickness at an interface thereof.

11. The method of claim 1 wherein the wall and the sacrificial material comprise a same primary material, the same primary material of the wall being doped with a substance, the same primary material of the sacrificial material comprising less, if any, of the substance than does the same primary material of the wall.

12. The method of claim 11 wherein the primary material is polysilicon and the substance is one of B, C, O, or N.

13. The method of claim 1 comprising etching completely through a portion of the wall to reduce its width prior to forming the upper portion.

14. The method of claim 1 wherein forming the wall comprises:
forming a mask opening in masking material that is directly above the sacrificial material; and
one of ion implanting, plasma doping, or diffusion doping a substance through the mask opening into the sacrificial material directly there-below.

15. The method of claim 14 wherein,
the mask opening has a horizontal longitudinal outline the same as what-will-be the wall in a finished circuitry construction, the horizontal longitudinal of the mask opening being wider than what-will-be the wall in the finished circuitry construction, the one of ion implanting, plasma doping, or diffusion doping forming an initial wall that is wider than the wall in the finished circuitry construction; and
further comprising etching completely through a portion of the initial wall to reduce its width after the one of ion implanting, plasma doping, or diffusion doping and prior to forming the upper portion.

16. The method of claim 1 wherein forming the wall comprises:
forming a mask opening in masking material that is directly above the sacrificial material;
etching through the mask opening to form a horizontally-elongated wall-trench through the sacrificial material;
overfilling the wall-trench with material of the wall; and
removing the material of the wall back to at least a top surface of the sacrificial material.

17. The method of claim 1 wherein selectivity of the isotropically etching of the sacrificial material relative to the wall is at least 10:1.

18. The method of claim 1 wherein, during said replacing, the wall at least in part precludes any of the conducting material from being directly against any TAV that is in the TAV region of the one of the (a) and the (b) where the wall is in.

19. The method of claim 1 wherein, in a finished construction, one side of the wall is directly against the conducting material and another side of the wall is directly against insulator material that is in the TAV region of the one of the (a) and the (b) where the wall is in.

20. A memory array comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the channel-material strings directly electrically coupling with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings, the channel-material strings in the laterally-spaced memory blocks comprising part of a memory plane; and
a wall in the lowest conductive tier aside the conducting material, the wall being horizontally-elongated in the memory plane longitudinally-along one of the memory blocks, the one memory block being immediately-adjacent a through-array-via (TAV) region that is in the memory plane, the wall being along an edge of the one memory block that is closest to the TAV region that is in the memory plane.

21. The memory array of claim 20 wherein the wall has a top that is at or below a bottom of a next-lowest conductive tier that is directly above the lowest conductive tier.

22. The memory array of claim 20 wherein the wall has a bottom that is at or above a top of the conductor tier.

23. The memory array of claim 20 wherein,
the wall has a top that is at or below a bottom of a next-lowest conductive tier that is directly above the lowest conductive tier; and
the wall has a bottom that is at or above a top of the conductor tier.

24. The memory array of claim 20 wherein the wall is along all of the edge of the one memory block region that is closest to the TAV region.

Assignees

• Micron Technology Inc

Inventors

• Barclay M Jared
• Hopkins John D
• Hill Richard J
• Chary Indra V
• Thong Kar Wui

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title