Memory system for programming dummy data to a portion of a storage region in a program mode

Patent metadata

Field	Value
Publication number	US-12068047-B2
Application number	US-202117535771-A
Country	US
Kind code	B2
Filing date	Nov 26, 2021
Priority date	Jan 27, 2021
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

An operating method of a memory system includes storing normal data to a first storage area of a non-volatile memory in a first program mode among multiple program modes defined according to a number of bits stored in each memory cell; storing dummy data in the first storage area in at least one of the multiple program modes including the first program mode; and copying the normal data from the first storage area to a second storage area of the non-volatile memory based on dummy data stored in the first program mode.

First claim

What is claimed is:

1. An operating method of a memory system including a non-volatile memory, the operating method comprising:
storing normal data in a first storage area of the non-volatile memory in a first program mode among multiple program modes defined according to a number of bits stored in a memory cell of the non-volatile memory;
storing dummy data in the first storage area in at least one of the multiple program modes; and
copying the normal data from the first storage area to a second storage area of the non-volatile memory based on the dummy data stored in the first program mode,
wherein, in the first program mode, at least two bits are stored in the memory cell of the non-volatile memory, and
wherein the storing the dummy data in the first storage area in the at least one of the multiple program modes is performed based on a time period between a time when the first storage area is erased and a time when the first storage area is stored with the normal data.

2. The operating method of claim 1 , wherein the first storage area comprises memory cells connected to a plurality of word lines including a first word line and a second word line, the first word line being distinguished from the second word line based on a number of fail bits involved in a read operation, and
wherein the storing the dummy data in the first storage area in one of the multiple program modes comprises:
storing the dummy data in at least one memory cell connected to the first word line in the first program mode; and
storing the dummy data in at least one memory cell connected to the second word line in at least one second program mode that is different from the first program mode.

3. The operating method of claim 2 , wherein a number of fail bits in a read operation of the first word line is greater than a number of fail bits in a read operation of the second word line, and
wherein a number of bits stored in each memory cell in the first program mode is greater than a number of bits stored in each memory cell in the second program mode.

4. The operating method of claim 1 , wherein the first storage area includes memory cells connected to a plurality of word lines vertically stacked on a substrate, and
wherein the storing the dummy data in the first storage area in the one of the multiple program modes comprises storing the dummy data in memory cells connected to at least one word line in the first program mode, the at least one word line being adjacent to the substrate among the plurality of word lines.

5. The operating method of claim 4 , wherein the storing the dummy data in the first storage area in the one of the multiple program modes comprises storing the dummy data in memory cells connected to a word line in at least one second program mode that is different from the first program mode, the word line being formed above the at least one word line among the plurality of word lines.

6. The operating method of claim 1 , wherein the copying the normal data from the first storage area to the second storage area of the non-volatile memory based on the dummy data stored in the first program mode comprises:
reading the dummy data stored in the first program mode;
counting a number of fail bits in the read dummy data; and
copying the normal data from the first storage area to the second storage area based on a result of comparing the number of fail bits with a reference number.

7. The operating method of claim 1 , wherein the dummy data is stored in an entire region of the first storage area where the normal data is not stored.

8. A memory controller for controlling a non-volatile memory comprising a plurality of storage areas each comprising at least one memory cell, the memory controller comprising:
a host interface configured to provide an interface with a host; and
at least one processor configured to implement a program operation controller configured to control the non-volatile memory to store normal data received from the host in a first storage area in a first program mode among multiple program modes defined according to a number of bits stored in a memory cell of the non-volatile memory,
wherein the program operation controller is further configured to control the non-volatile memory to store dummy data in the first storage area in the first program mode in which at least two bits are stored in the memory cell of the non-volatile memory, and
wherein the at least one processor is further configured to implement an erase-program interval (EPI) detector configured to obtain an EPI indicating a time period between a time when each of the plurality of storage areas is erased and a time when the each of the plurality of storage areas is stored with the normal data.

9. The memory controller of claim 8 ,
wherein the program operation controller is further configured to output information about the multiple program modes to the non-volatile memory, and store the dummy data to the first storage area based on the EPI of the first storage area.

10. The memory controller of claim 8 , further comprising a memory storing a program mode table indicating a program mode corresponding to each of a plurality of word lines connected to memory cells included in the first storage area,
wherein the program operation controller is further configured to control the non-volatile memory to store the dummy data in the first storage area in at least one program mode, among the multiple program modes, determined based on the program mode table.

11. The memory controller of claim 10 , wherein the program mode table matches the first program mode with a first word line having a number of fail bits exceeding a reference number, the fail bits occurring in a read operation.

12. The memory controller of claim 11 , wherein the program mode table matches other word lines than the first word line with at least one second program mode allowing a smaller number of bits to be stored in a memory cell than the first program mode.

13. The memory controller of claim 8 , wherein the at least one processor is further configured to implement a read reclaim controller configured to copy the normal data from the first storage area to a second storage area based on the dummy data stored in the first storage area in the first program mode.

14. The memory controller of claim 13 , wherein the read reclaim controller is configured to read the dummy data stored in the first program mode, count a number of fail bits in the read dummy data, and copy the normal data from the first storage area to the second storage area based on a result of comparing the number of fail bits with a reference number.

15. A memory system comprising:
a memory device comprising a first storage area and a second storage area; and
at least one processor configured to implement a memory controller configured to control the memory device to store normal data received from a host in the first storage area in a first program mode among multiple program modes defined according to a number of bits stored in a memory cell of the first storage area, and control the memory device to store dummy data in the first storage area in the first program mode and at least one second program mode that is different from the first program mode,
wherein the memory controller is further configured to control the memory device to store the dummy data in the first storage area based on a result of comparing a reference time with a time period between a time when the first storage area is erased and a time when the first storage area is stored.

16. The memory system of claim 15 , wherein the fi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Sukeun
• Seo Junho
• Lee Dogyeong
• Lee Juwon

Classifications

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title