Proxy wordline stress for read disturb detection

Patent metadata

Field	Value
Publication number	US-9741444-B2
Application number	US-201715483169-A
Country	US
Kind code	B2
Filing date	Apr 10, 2017
Priority date	Sep 11, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.

First claim

What is claimed is:

1. A method for read disturb detection, the method comprising:
storing a predetermined value instead of host data in a memory cell of a proxy word line of a block of non-volatile memory;
applying a read proxy voltage to a gate of the memory cell of the proxy word line if data is read from a selected memory cell of the block and the selected memory cell is not adjacent to the cell of the proxy word line; and
determining a read disturb of the block by comparing the predetermined value with a value read from the memory cell of the proxy word line.

2. The method of claim 1 further comprising applying a read pass voltage to control gates of transistors in cells that are adjacent to the selected memory cell if the data is read from the selected memory cell, wherein the read pass voltage is substantially the same as the read proxy voltage.

3. The method of claim 1 further comprising applying a read compare voltage to a control gate of the selected memory cell if the data is read from the selected memory cell, wherein the read compare voltage is less than the read proxy voltage.

4. The method of claim 1 , wherein applying the read proxy voltage comprises applying the read proxy voltage if the block is open, but not if the block is closed.

5. The method of claim 1 , wherein determining the read disturb comprises counting, during a wear leveling read scan, a number of zeros stored in memory cells coupled to the proxy word line, wherein the proxy word line is a dummy word line, wherein the block is a first block, wherein storing the predetermined value comprises erasing the memory cells coupled to the proxy word line; and wherein the method further comprises:
copying data from the first block to a second block that has a same cell level as the first block if the number of zeros exceeds a threshold value, else folding the data from the first block to a third block having a higher cell level than the first block.

6. The method of claim 1 , wherein determining the read disturb comprises counting, prior to closing the block, a number of zeros stored in memory cells coupled to the proxy word line, wherein the proxy word line is the last unprogrammed word line of the block, wherein storing the predetermined value comprises erasing the memory cells coupled to the proxy word line, wherein the block is a first block; and wherein the method further comprises:
copying data from the first block to a second block that has a same cell level as the first block if the number of zeros exceeds a threshold value, else closing the block by writing host data to the memory cells coupled to the proxy word line.

7. The method of claim 1 , wherein applying the read proxy voltage comprises applying the read proxy voltage even if the block is closed, the method further comprising:
sampling, during a wear leveling read scan, memory cells coupled to the proxy word line for error code correction (ECC), and wherein the block is a first block; and
copying data from the first block to a second block that has a same cell level as the first block if ECC exceeds a threshold value, else folding the data from the first block to a third block having a higher cell level than the first block.

Assignees

• Sandisk Technologies Llc

Inventors

• Reusswig Philip
• Singidi Harish
• Raghu Deepak
• Dusija Gautam
• Koh Pao-Ling
• Avila Chris

Classifications

• G11C16/3422 Primary

  Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem · CPC title

• G06F11/1072

  in multilevel memories · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title