Memory system with multiple programming modes

Patent metadata

Field	Value
Publication number	US-9852802-B2
Application number	US-201615141389-A
Country	US
Kind code	B2
Filing date	Apr 28, 2016
Priority date	Sep 9, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device has a first program mode and a second program mode. The second program mode programs data to have a larger read margin than the first program mode. The memory controller controls the nonvolatile memory device to program the data according to the second program mode for a read reclaim operation.

First claim

What is claimed is:

1. A memory system comprising:
a nonvolatile memory device having a first program mode and a second program mode, wherein the second program mode programs data to have a larger read margin than the first program mode; and
a memory controller that controls the nonvolatile memory device to program the data according to the second program mode for a read reclaim operation, wherein:
each of the first program mode and the second program mode programs the data through multi-stage programming, and
each i th stage of the multi-stage programming, where i is an integer greater than zero, is the same for both the first program mode and the second program mode, but the second program mode has more stages of the multi-stage programming than does the first program mode.

2. The memory system of claim 1 , wherein the first program mode is applied to programming operations other than the read reclaim operation.

3. The memory system of claim 1 , wherein the nonvolatile memory device comprises a three-dimensional memory array.

4. The memory system of claim 1 , wherein an Incremental Step Pulse Programming (ISPP) technique is applied for each of the first program mode and the second program mode.

5. The memory system of claim 1 , wherein each of the first program mode and the second program mode programs multi-bit data in one memory cell.

6. The memory system of claim 1 , wherein the data programmed according to the second program mode is retrieved from a first block of memory cells of the nonvolatile memory device and programmed within a second block of the memory cells that differs from the first block of memory cells.

7. The memory system of claim 1 , wherein:
the memory controller controls the nonvolatile memory device to program each of the memory cells to one of multiple programming states, and
a voltage margin between voltage threshold distributions of adjacent programming states is greater for the memory cells of the nonvolatile memory device programmed according to the second program mode than for those programmed according to the first program mode.

8. The memory system of claim 1 , wherein the memory controller controls the nonvolatile memory device to program the data within selected memory cells of the nonvolatile memory device according to the second program mode when a bit error rate corresponding to the data, as read from the nonvolatile memory device, exceeds a predetermined rate.

9. A memory system comprising:
a nonvolatile memory device having a normal program mode and a reclaim program mode, wherein the reclaim program mode programs data to have a larger read margin than the normal program mode; and
a memory controller that detects error bits of read data readout from the nonvolatile memory device and controls the nonvolatile memory device to program the read data into a free block of the nonvolatile memory device in the reclaim program mode when a number of detected error bits exceeds a reference value, wherein:
each of the normal program mode and the reclaim program mode programs the data through multi-stage programming, and
each i th stage of the multi-stage programming, where i is an integer greater than zero, is the same for both the normal program mode and the reclaim program mode, but the reclaim program mode has more stages of the multi-stage programming than does the normal program mode.

10. The memory system of claim 9 , wherein an Incremental Step Pulse Programming (ISPP) technique is applied for each of the reclaim program mode and the normal program mode.

11. The memory system of claim 9 , wherein the nonvolatile memory device comprises a three-dimensional memory array.

12. The memory system of claim 9 , wherein the data programmed according to the reclaim program mode is retrieved from a first block of memory cells of the nonvolatile memory device and programmed within a second block of the memory cells that differs from the first block of memory cells.

13. The memory system of claim 9 , wherein:
the memory controller controls the nonvolatile memory device to program each of memory cells of the nonvolatile memory device to one of multiple programming states, and
a voltage margin between voltage threshold distributions of adjacent programming states is greater for the memory cells of the nonvolatile memory device programmed according to the reclaim program mode than for those programmed according to the normal program mode.

14. A memory system comprising:
a nonvolatile memory device comprising a plurality of memory cells; and
a memory controller that controls the nonvolatile memory device to program data within selected ones of the memory cells of the nonvolatile memory device according to each of a general programming mode and a read reclaim mode, wherein data programmed according to the read reclaim mode has a narrower voltage threshold distribution within the selected memory cells than data programmed according to the general programming mode, wherein:
each of the general programming mode and the read reclaim mode programs the data through multi-stage programming, and
each stage of the multi-stage programming is the same for both the general programming mode and the read reclaim mode, except a last stage of the multi-stage programming.

15. The memory system of claim 14 , wherein the data programmed according to the read reclaim mode is retrieved from a first block of the memory cells of the nonvolatile memory device and programmed within a second block of the memory cells that differs from the first block of memory cells.

16. The memory system of claim 14 , wherein:
the memory controller controls the nonvolatile memory device to program each of the memory cells to one of multiple programming states, and
a voltage margin between voltage threshold distributions of adjacent programming states is greater for the memory cells of the nonvolatile memory device programmed according to the read reclaim mode than for those programmed according to the general programming mode.

17. The memory system of claim 14 , wherein the memory controller controls the nonvolatile memory device to program the data within the selected memory cells according to the read reclaim mode when a bit error rate corresponding to the data, as read from the nonvolatile memory device, exceeds a predetermined rate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Sang-Wook

Classifications

• G06F3/0634 Primary

  by changing the state or mode of one or more devices · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G06F3/0611

  in relation to response time · CPC title