Memory system for performing fail bit check operation and operating method of the same

Patent metadata

Field	Value
Publication number	US-10073660-B2
Application number	US-201615299205-A
Country	US
Kind code	B2
Filing date	Oct 20, 2016
Priority date	Jun 27, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Provided herein are a memory system and method of operating the memory system, which have improved reliability. A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks, the method comprising generating a program command and a program address for performing a program operation on at least one page included in an open block, among the plurality of memory blocks, reading data from the at least one page corresponding to the program address and transmitting the program command and the program address to the semiconductor memory device when the number of fail bits included in data read from the at least one page is equal to or less than a first reference value.

First claim

What is claimed is:

1. A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks, the method comprising:
generating a program command and a program address for performing a program operation on at least one page included in an open block, among the plurality of memory blocks;
reading data from the at least one page corresponding to the program address; and
transmitting the program command and the program address to the semiconductor memory device when a number of fail bits included in data read from the at least one page is equal to or less than a first reference value.

2. The method according to claim 1 , further comprising:
generating a program command and a program address for performing a program operation on memory blocks other than the open block when the number of fail bits included in the page data is greater than the first reference value.

3. The method according to claim 2 , further comprising:
programming dummy data in at least one empty page included in the open block; and
setting the open block as a closed block.

4. The method according to claim 1 , wherein the first reference value indicates a preset number of fail bits per kilobyte (kB).

5. The method according to claim 1 , wherein the at least one page corresponds to a word line adjacent to any one of a drain select line and a source select line of the open block.

6. The method according to claim 1 , wherein the reading of the data from the at least one page comprises:
transmitting a read command for the at least one page to the semiconductor memory device; and
receiving data, obtained by reading the data from the at least one page using a first fail check voltage, from the semiconductor memory device.

7. The method according to claim 6 , wherein the first fail check voltage has a voltage level for verifying a threshold voltage corresponding to an erase state.

8. The method according to claim 1 , further comprising:
reading data from at least one programmed page when the program operation based on the program command is completed; and
moving data of a memory block including the at least one programmed page to a memory block other than the open block when a number of fail bits included in data read from the at least one programmed page is greater than a second reference value.

9. The method according to claim 8 , wherein the second reference value has a value greater than the first reference value.

10. The method according to claim 8 , wherein the reading of the data from at least one programmed page comprises:
transmitting a read command for the at least one programmed page to the semiconductor memory device; and
receiving data, obtained by reading data from the at least one programmed page using a second fail check voltage, from the semiconductor memory device.

11. The method according to claim 10 , wherein the second fail check voltage is a read voltage for classifying states of memory cells included in the at least one programmed page into an erase state and a program state.

12. The method according to claim 8 , wherein the at least one programmed page is programmed last in the program operation, among a plurality of pages included in the open block.

13. A controller for controlling a semiconductor memory device including a plurality of memory blocks, the controller comprising:
a processor configured to generate a first program command and a first program address for performing a program operation on at least one page included in an open block among the plurality of memory blocks, to read data from the at least one page corresponding to the program address and to transmit the program command and the program address to the semiconductor memory device according to a number of fail bits included in data read from the at least one page; and
a memory interface configured to communicate with the semiconductor memory device according to a control of the processor.

14. The controller according to claim 13 ,
wherein the processor generates a second program command and a second program address for performing a program operation on a memory block other than the open block among the plurality of memory blocks when the number of fail bits included in data read from the at least one page is greater than a first reference value.

15. The controller according to claim 14 , further comprising:
a memory block management unit configured to manage memory block state information indicating states of the plurality of memory blocks,
wherein:
the processor programs dummy data in at least one empty page included in the open block, and
the memory block management unit sets the open block as a closed block.

16. The controller according to claim 13 ,
wherein the processor transmits the first program command and the first program address to the semiconductor memory device when the number of fail bits included in data read from the at least one page is equal to or less than a first reference value, reads data from at least one page included in the open block after the program operation is performed, and moves data of the open block to a memory block other than the open block when a number of fail bits included in data read from the at least one page included in the open block after the program operation is performed is greater than a second reference value.

17. The controller according to claim 16 , wherein the second reference value has a value greater than the first reference value.

18. The controller according to claim 16 , further comprising:
a memory block management unit configured to manage memory block state information indicating states of the plurality of memory blocks,
wherein:
the processor erases the open block after the data of the open block is moved to the memory block other than the open block, and
the memory block management unit sets the open block as a free block.

Assignees

• Sk Hynix Inc

Inventors

• Park Byoung Jun
• Park Seong Jo
• Lee Kang Jae

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/08

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0614

  Improving the reliability of storage systems · CPC title