Variable resistance memory device

Patent metadata

Field	Value
Publication number	US-12063876-B2
Application number	US-202117399194-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Aug 13, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

A variable resistance memory device includes a variable resistance layer and a first conductive element and a second conductive element which are spaced apart from each other on the variable resistance layer. The variable resistance layer may include a first layer and a second layer on the first layer. The first layer includes a ternary or more metal oxide containing two or more metal materials having different valences. The second layer may include silicon oxide. The variable resistance memory device may have a wide range of resistance variation due to the metal oxide in which oxygen vacancies are easily formed. The first conductive element and the second conductive element, in response to an applied voltage, may be configured to form a current path in a direction perpendicular to a direction in which the first layer and the second direction are stacked.

First claim

What is claimed is:

1. A variable resistance memory device comprising:
a variable resistance layer including a first layer and a second layer on the first layer, the first layer including a ternary or more metal oxide containing two or more metal materials having different valences, and the second layer including an oxide;
a first conductive element on the variable resistance layer; and
a second conductive element on the variable resistance layer and spaced apart from the first conductive element,
the first conductive element and the second conductive element, in response to an applied voltage, being configured to form a current path in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

2. The variable resistance memory device of claim 1 , wherein the first conductive element and the second conductive element contact the second layer.

3. The variable resistance memory device of claim 1 , wherein the second layer includes a silicon oxide.

4. The variable resistance memory device of claim 1 , wherein the metal oxide includes Rb, Ti, Ba, Zr, Ca, Hf, Sr, Sc, B, Mg, Al, K, Y, La, Si, Be, Nb, Ni, Ta, W, V, La, Gd, Cu, Mo, Cr, or Mn.

5. The variable resistance memory device of claim 1 , wherein the metal oxide is represented by (M1) x (M2) y O z , M1 and M2 are each a metal element, a valance of M1 is greater than that of M2, and x≥y is satisfied.

6. The variable resistance memory device of claim 1 , wherein the metal oxide includes AlTiO, HfAlO, HfMgO, HfKO, HfCaO, HfScO, HfSrO, HfBaO, HfBO, HfYO, HfLaO, AlZrO, AlSiO, MgSiO, MgZrO, ZrNbO, HfNbO, or HfTaO.

7. The variable resistance memory device of claim 1 , wherein the metal oxide is HfAlO, HfMgO, HfKO, HfCaO, HfScO, HfSrO, or HfBaO.

8. The variable resistance memory device of claim 1 , wherein the two or more metal materials included in the metal oxide are selected so that a trap depth of the variable resistance layer is less than 1 eV.

9. The variable resistance memory device of claim 1 , wherein a thickness of the first layer is less than or equal to about 100 nm.

10. The variable resistance memory device of claim 1 , wherein a thickness of the first layer is in a range of about 1 nm to about 10 nm.

11. The variable resistance memory device of claim 1 , wherein a thickness of the second layer is less than or equal to about 5 nm.

12. A variable resistance memory device comprising:
an insulating layer;
a variable resistance layer on the insulating layer, the variable resistance layer including a first layer and a second layer on the first layer,
the first layer including a ternary or more metal oxide containing two or more metal materials having different valences, and the second layer including an oxide;
a channel layer on the variable resistance layer;
a gate insulating layer on the channel layer; and
a plurality of gate electrodes and a plurality of insulators which are alternately and repeatedly disposed on the gate insulating layer in a first direction parallel to the channel layer.

13. The variable resistance memory device of claim 12 , wherein the second layer is in contact with the channel layer, and the oxide included in the second layer is an oxide of a material of the channel layer.

14. The variable resistance memory device of claim 12 , wherein the channel layer includes polysilicon (poly-Si), and the second layer includes a silicon oxide.

15. The variable resistance memory device of claim 8 , wherein the metal oxide includes Rb, Ti, Ba, Zr, Ca, Hf, Sr, Sc, Mg, Al, Si, Be, Nb, Ni, Ta, W, V, La, Gd, Cu, Mo, Cr, or Mn.

16. The variable resistance memory device of claim 12 , wherein the metal oxide is represented by (M1) x (M2) y O z , M1 and M2 are each a metal element, a valance of M1 is greater than that of M2, and x≥y is satisfied.

17. The variable resistance memory device of claim 12 , wherein the metal oxide includes AlTiO, HfAlO, HfMgO, HfKO, HfCaO, HfScO, HfSrO, HfBaO, HfBO, HfYO, HfLaO, AlZrO, AlSiO, MgSiO, MgZrO, ZrNbO, HfNbO, or HfTaO.

18. The variable resistance memory device of claim 12 , wherein the metal oxide is HfAlO, HfMgO, HfKO, HfCaO, HfScO, HfSrO, or, HfBaO.

19. The variable resistance memory device of claim 12 , wherein the two or more metal materials included in the metal oxide are selected so that a trap depth of the variable resistance layer is less than 1 eV.

20. The variable resistance memory device of claim 12 , wherein a thickness of the first layer is less than or equal to about 100 nm.

21. The variable resistance memory device of claim 12 , wherein a thickness of the first layer ranges from about 1 nm to about 10 nm.

22. The variable resistance memory device of claim 12 , wherein a thickness of the second layer is less than or equal to about 5 nm.

23. The variable resistance memory device of claim 12 , wherein
the insulating layer has a cylindrical shape extending in the first direction,
the variable resistance layer, the channel layer, and the gate insulating layer sequentially surround the insulating layer to provide a cylinder-shell shape, and
the plurality of gate electrodes and the plurality of insulators surround the gate insulating layer alternately in the first direction.

24. The variable resistance memory device of claim 23 , wherein a sum of lengths of a gate electrode and an insulator in the first direction, which are disposed adjacent to each other among the plurality of gate electrodes and the plurality of insulators, is less than about 20 nm.

25. The variable resistance memory device of claim 24 , further comprising:
a drain region and a source region contacting opposite end portions of the channel layer and the variable resistance layer in the first direction, respectively.

26. The variable resistance memory device of claim 25 , further comprising:
a bit line connected to the drain region;
a source line connected to the source region; and
a plurality of word lines connected to the plurality of gate electrodes, respectively.

27. An electronic device, comprising:
the variable resistance memory device of claim 12 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seyun
• Kim Doyoon
• Kim Yumin
• Kim Jinhong
• Mizusaki Soichiro
• Cho Youngjin

Classifications

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/253

  having three or more electrodes, e.g. transistor-like devices · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10B63/34 Primary

  of the vertical channel field-effect transistor type · CPC title