Three dimensional package for semiconductor devices and external components

Patent metadata

Field	Value
Publication number	US-12062597-B2
Application number	US-202318297751-A
Country	US
Kind code	B2
Filing date	Apr 10, 2023
Priority date	Dec 28, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

First claim

What is claimed is:

1. A method, comprising:
forming a semiconductor device die with bond pads on a surface of the semiconductor device die;
forming a seed layer on the surface of the semiconductor device die;
depositing a photoresist layer on the seed layer;
forming openings in the photoresist layer, the openings exposing the seed layer;
forming post interconnects in the openings, the post interconnects including a conductive material and extending away from the surface;
removing the photoresist layer;
removing the seed layer uncovered by the post interconnects;
mounting the semiconductor device die to a die mount portion of a package substrate, the package substrate having conductive leads spaced from the die mount portion;
forming electrical connections between at least one bond pad of the semiconductor device die and a corresponding one of the conductive leads of the package substrate; and
covering the semiconductor device die, a portion of the package substrate, the electrical connections, and a portion of the post interconnects with a dielectric material to form a packaged semiconductor device, the post interconnects extending through the dielectric material, wherein ends of the post interconnects are exposed from the dielectric material and form terminals of the packaged semiconductor device.

2. The method of claim 1 , wherein the electrical connections include bond wires.

3. The method of claim 1 , wherein forming the post interconnects includes plating a conductive metal on the seed layer.

4. The method of claim 3 , wherein the conductive metal includes copper, gold, palladium, platinum, silver, nickel, tin, or alloys thereof.

5. The method of claim 1 , further comprising:
forming an internal redistribution layer between the semiconductor device die and the post interconnects, the internal redistribution layer including conductors that couple the bond pads to the post interconnects.

6. The method of claim 1 , further comprising:
mounting a component on the packaged semiconductor device, the component being electrically coupled to the ends of the post interconnects.

7. The method of claim 1 , further comprising:
forming an external redistribution layer on the ends of the post interconnects, the external redistribution layer including conductors coupled to the post interconnects.

8. The method of claim 7 , further comprising:
mounting a component on the external redistribution layer, the component being electrically coupled to the external redistribution layer.

9. A method, comprising:
forming first and second bond pads on a surface of a semiconductor device die;
forming a post interconnect connected to the first bond pad through a seed layer, wherein the post interconnect has a first footprint and the seed layer has a second footprint that is substantially same as the first footprint;
mounting the semiconductor device die with the post interconnect to a die mount portion of a lead frame, the surface of the semiconductor device die facing away from the lead frame;
forming an electrical connection coupling the second bond pad to a conductive lead of the lead frame; and
covering the semiconductor device die, a portion of the lead frame, the electrical connection, and a portion of the post interconnect with a dielectric material, wherein an end of the post interconnect is exposed from the dielectric material.

10. The method of claim 9 , wherein the electrical connection includes a bond wire.

11. The method of claim 9 , wherein forming the post interconnect includes plating a conductive metal on the seed layer.

12. The method of claim 9 , wherein forming the post interconnect includes coating the end of the post interconnect with gold, nickel, tin, palladium, or a combination thereof.

13. The method of claim 9 , further comprising:
forming a spacer on the die mount portion such that the spacer is disposed between the semiconductor device die and the die mount portion.

14. The method of claim 9 , further comprising:
mounting a component to the end of the post interconnect, the component being electrically connected to the end of the post interconnect, wherein the component includes a passive device, a sensor, a laser device, or an integrated circuit.

15. The method of claim 14 , wherein the component is directly connected to the end of the post interconnect.

16. The method of claim 14 , wherein the component is connected to the end of the post interconnect through a solder ball.

17. The method of claim 9 , wherein the post interconnect has a cross-sectional area that is constant throughout its height.

18. The method of claim 9 , wherein:
the post interconnect has a portion contacting the seed layer, the portion having a first cross-sectional area; and
the end of the post interconnect has a second cross-sectional area greater than the first cross-sectional area.

19. The method of claim 9 , wherein the seed layer includes copper or copper alloy.

20. The method of claim 9 , wherein the post interconnect includes copper, gold, palladium, platinum, nickel, silver, tin, or a combination thereof.

21. The method of claim 9 , further comprising:
forming a redistribution layer between the semiconductor device die and the post interconnect, the redistribution layer including a first conductor that couples the first bond pad to the post interconnect.

22. The method of claim 21 , wherein the redistribution layer further includes a second conductor that couples the second bond pad to the electrical connection.

23. The method of claim 9 , further comprising:
forming a redistribution layer on the end of the post interconnect, the redistribution layer including a conductor electrically connected to the post interconnect.

24. The method of claim 23 , further comprising:
mounting a component on the redistribution layer, the component connected to the conductor of the redistribution layer.

25. The method of claim 23 , further comprising:
forming an adhesive layer disposed between the redistribution layer and the end of the post interconnect.

26. The method of claim 23 , further comprising:
forming a solder ball on the end of the post interconnect such that the conductor of the redistribution layer is connected to the post interconnect through the solder ball.

Assignees

• Texas Instruments Inc

Inventors

• Manack Christopher Daniel
• Koduri Sreenivasan Kalyani

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W74/016

  using moulds · CPC title

• H10W70/467

  Multilayered additional interconnections · CPC title

• H10W70/417

  Bonding materials between chips and die pads · CPC title