Patch on interposer architecture for low cost optical co-packaging

Patent metadata

Field	Value
Publication number	US-12061371-B2
Application number	US-202017131621-A
Country	US
Kind code	B2
Filing date	Dec 22, 2020
Priority date	Dec 22, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.

First claim

What is claimed is:

1. A semiconductor package, comprising:
an interposer;
a photonics die having a front-side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the front-side facing away from the interposer;
a patch substrate mounted on the interposer adjacent to the photonics die;
a logic die mounted on the patch substrate with an overhang past an edge of the patch substrate, and the overhang is attached to the solder bumps of the photonics die; and
an integrated heat spreader (IHS) over the logic die such that the photonics die does not directly contact the IHS.

2. The semiconductor package of claim 1 , further comprising a copper slug within a cavity in the interposer beneath the photonics die to extract heat away from the photonics die.

3. The semiconductor package of claim 1 , further comprising a copper pillar array within a cavity in the interposer beneath the photonics die to extract heat away from the photonics die.

4. The semiconductor package of claim 1 , wherein a body of the patch substrate has a slot therein, the patch substrate mounted to the interposer such that the slot surrounds one end of the photonics die.

5. The semiconductor package of claim 4 , wherein the logic die is mounted on the patch substrate and covers the slot so that a portion of the logic die is over the photonics die and is attached to the solder bumps of the photonics die.

6. The semiconductor package of claim 1 , further comprising dummy silicon mounted on the interposer directly beneath the photonics die.

7. The semiconductor package of claim 6 , wherein the dummy silicon is attached to the interposer with a first die attach film, and is attached to the photonics die with a second die attach film.

8. The semiconductor package of claim 6 , further comprising at least one of a copper slug or a copper pillar array within a cavity in the interposer beneath dummy silicon.

9. The semiconductor package of claim 1 , further comprising one end of a fiber array attached to the on-chip fiber connector on the photonics die and a second end of the fiber array attached to a second fiber connector.

10. The semiconductor package of claim 9 , wherein the second fiber connector is spaced apart from the photonics die and is mounted between the interposer and the IHS.

11. The semiconductor package of claim 9 , wherein the fiber connector comprises a set of V-grooves on the photonics die to connect to a fiber array.

12. The semiconductor package of claim 9 , wherein the on-chip fiber connector is directly attached to the photonics die over the set of V-grooves on the photonics die.

13. The semiconductor package of claim 1 , further comprising a panel carrier mounted on the interposer adjacent to the patch substrate, and the photonics die is attached to the panel carrier with the solder bumps facing up.

14. The semiconductor package of claim 1 , wherein the fiber connector includes an alignment hole to guide in an external fiber connector, wherein a first magnet is placed on one side of the alignment hole and a second magnet is placed on a second side of the alignment hole.

15. The semiconductor package of claim 14 , further comprising a third magnet in the IHS in alignment over the first magnet and the second magnet.

16. A semiconductor package, comprising:
a photonics die mounted upside down on an interposer with a front side of the photonics die including a V-groove fiber connector and solder bumps facing away from the interposer;
a patch substrate mounted on the interposer adjacent to the photonics die;
a field-programmable gate array (FPGA) die mounted on the patch substrate with an overhang past an edge of the patch substrate, and the overhang is attached to the solder bumps of the photonics die; and
an integrated heat spreader (IHS) over the FPGA die such that the photonics die does not directly contact the IHS.

17. The semiconductor package of claim 16 , further comprising a copper slug within a cavity in the interposer beneath the photonics die to extract heat away from the photonics die.

18. The semiconductor package of claim 16 , further comprising a copper pillar array within a cavity in the interposer beneath the photonics die to extract heat away from the photonics die.

19. The semiconductor package of claim 16 , wherein a body of the patch substrate has a slot therein, the patch substrate mounted to the interposer such that the slot surrounds one end of the photonics die.

20. The semiconductor package of claim 19 , wherein the FPGA die is mounted on the patch substrate and covers the slot so that a portion of the FPGA die is over the photonics die and is attached to the solder bumps of the photonics die.

21. The semiconductor package of claim 16 , further comprising dummy silicon mounted on the interposer directly beneath the photonics die.

22. The semiconductor package of claim 21 , further comprising at least one of a copper slug or a copper pillar array within a cavity in the interposer beneath dummy silicon.

23. The semiconductor package of claim 16 , further comprising one end of a fiber array attached to the V-groove connector on the photonics die and a second end of the fiber array attached to a second fiber connector.

24. A method of fabricating a semiconductor package, the method comprising:
attaching a photonics die on an interposer with a die attach film, wherein the photonics die has a front-side having an on-chip fiber connector and solder bumps, the photonics die attached to the interposer with the front-side facing away from the interposer;
attaching a patch substrate to the interposer adjacent to the photonics die using thermal compression bonding;
attaching a logic die to the patch substrate with an overhang past an edge of the patch substrate such that the overhang is attached to the solder bumps of the photonics die; and
attaching an integrated heat spreader (IHS) to the logic die such that the photonics die does not directly contact the IHS.

25. The method of claim 24 , further comprising forming a copper slug or a copper pillar array in the interposer beneath the photonics die.

Assignees

• Intel Corp

Inventors

• Li Xiaoqian
• Deshpande Nitin
• Karhade Omkar
• Mahajan Ravindranath V

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title