Compact optical transceiver by hybrid multichip integration

Patent metadata

Field	Value
Publication number	US-9921379-B2
Application number	US-201715481994-A
Country	US
Kind code	B2
Filing date	Apr 7, 2017
Priority date	Mar 10, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.

First claim

What is claimed is:

1. An optical transceiver by hybrid multichip integration comprising:
a Si-photonics chip attached on a PCB;
a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB;
a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps; and
a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps;
wherein the Si-photonics chip comprises a modulator and photo diodes embedded inside an SOI wafer and respectively coupled to multiple first conductive pads and multiple second conductive pads formed on a top surface of the SOI wafer;
wherein the first set of bumps comprises one or more first signal bumps alternatively arranged with one or more first ground bumps in a staggered manner along a nominal direction, each first signal bump being soldered to one of the first conductive pads connected to a first transmission line on the Si-photonics chip and each first ground bump being soldered to a neighboring one of the first conductive pads connected to a first GND plane on the Si-photonics chip, the first transmission line having a first width substantially smaller than a width of the first GND plane; and
wherein the first GND plane comprises a cut-out portion around corresponding one of the first conductive pads such that the first GND plane on the Si-photonics chip substantially not overlaps with another GND plane on the driver chip, resulting in reduced parasitic capacitance and enhanced inductance associated with the first ground bump connection between the driver chip at top to the Si-photonics chip at bottom connected to the modulator embedded therein.

2. An optical transceiver by hybrid multichip integration comprising:
a Si-photonics chip attached on a PCB;
a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB;
a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps; and
a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps;
wherein the Si-photonics chip comprises a modulator and photo diodes embedded inside an SOI wafer and respectively coupled to multiple first conductive pads and multiple second conductive pads formed on a top surface of the SOI wafer;
wherein the first set of bumps comprises one or more first signal bumps alternatively arranged with one or more first ground bumps in a staggered manner along a nominal direction, each first signal bump being soldered to one of the first conductive pads connected to a first transmission line on the Si-photonics chip and each first ground bump being soldered to a neighboring one of the first conductive pads connected to a first GND plane on the Si-photonics chip, the first transmission line having a first width substantially smaller than a width of the first GND plane; and
wherein the second GND plane comprises a cut-out portion around corresponding one of the second conductive pads such that the second GND plane on the Si-photonics chip substantially not overlaps with another GND plane on the transimpedance amplifier module chip, resulting in reduced parasitic capacitance and enhanced inductance associated with the third ground bump connection between the transimpedance amplifier module chip at top to the Si-photonics chip at bottom connected to the photo diodes embedded therein.

3. The optical transceiver of claim 2 wherein the first set of bumps comprises one or more first signal bumps alternatively arranged with one or more first ground bumps in a staggered manner along a nominal direction, each first signal bump being soldered to one of the first conductive pads connected to a first transmission line on the Si-photonics chip and each first ground bump being soldered to a neighboring one of the first conductive pads connected to a first GND plane on the Si-photonics chip, the first transmission line having a first width substantially smaller than a width of the first GND plane.

4. The optical transceiver of claim 2 wherein each of the third and fourth set of bumps has a third pitch distance relative to a neighboring bump along the nominal direction and a fourth pitch distance relative to the same neighboring bump along a perpendicular direction, the third pitch distance being substantially equal to the fourth pitch distance.

5. The optical transceiver of claim 4 wherein each of the third and fourth set of bumps comprises a diameter as large as 50 μm with each of the first pitch distance and the second pitch distance being as small as 125 μm.

6. The optical transceiver of claim 1 wherein the Si-photonics chip further comprises multiple third conductive pads formed on the top surface configured to attach one or more laser diodes and respectively wire bonded to the PCB to receive DC current injections.

7. The optical transceiver of claim 6 wherein the Si-photonics chip further comprises multiple suspended couplers, some of the multiple suspended couplers being configured to couple with outputs of one or more laser diodes and others of the multiple suspended couplers being configured to couple with one or more optical fibers.

8. The optical transceiver of claim 1 further comprising a PAM4 encoder, a PAM4 decoder, and multiple AC coupling capacitors, respectively bonded on the PCB without any wire bonds.

9. The optical transceiver of claim 1 wherein each of the first TSV interposer and the second TSV interposer is fabricated using a high-resistance silicon substrate or glass substrate completely independent of the Si-photonics chip.

10. The optical transceiver of claim 2 wherein the Si-photonics chip further comprises multiple third conductive pads formed on the top surface configured to attach one or more laser diodes and respectively wire bonded to the PCB to receive DC current injections.

11. The optical transceiver of claim 10 wherein the Si-photonics chip further comprises multiple suspended couplers, some of the multiple suspended couplers being configured to couple with outputs of one or more laser diodes and others of the multiple suspended couplers being configured to couple with one or more optical fibers.

12. The optical transceiver of claim 2 further comprising a PAM4 encoder, a PAM4 decoder, and multiple AC coupling capacitors, respectively bonded on the PCB without any wire bonds.

13. The optical transceiver of claim 2 wherein each of the first TSV interposer and the second TSV interposer is fabricated using a high-resistance silicon substrate or glass substrate completely independent of the Si-photonics chip.

14. The optical transceiver of claim 2 wherein the first transmission line comprises a first trace section connected directly to the corresponding one of the first conductive pads, the first trace section having a reduced width of at least half of the first width resulting in reduced parasitic capacitance and enhanced inductance associated with the first signal bump connection between the driver chip at top to the Si-photonics chip at bottom connected to the modulator embedded therein.

Assignees

• Inphi Corp

Inventors

• Ding Liang
• Nagarajan Radhakrishnan L
• Coccioli Roberto

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07253

  changes in shapes · CPC title