Package formation methods including coupling a molded routing layer to an integrated routing layer

Patent metadata

Field	Value
Publication number	US-12057364-B2
Application number	US-202217991503-A
Country	US
Kind code	B2
Filing date	Nov 21, 2022
Priority date	Dec 22, 2017
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

First claim

The invention claimed is:

1. A method, comprising:
coupling an integrated routing layer over upward facing active surfaces of a number of dies to form a number of fan out batch process carrier level semiconductor devices on a fan out batch process carrier to a first width, wherein coupling the integrated routing layer to the number of dies to form the number of fan out batch process carrier level semiconductor devices comprises electroplating pillars directly onto contacts on a surface of a die of the number of dies;
singulating the fan out batch process carrier level semiconductor devices from the fan out batch process carrier; and
coupling a molded routing layer to one or more of the fan out batch process carrier level semiconductor devices, wherein the molded routing layer extends to a second width wider than the first width.

2. The method of claim 1 , wherein coupling the integrated routing layer to the number of dies to form the number of fan out batch process carrier level semiconductor devices comprises coupling the integrated routing layer to the number of dies to form a number of fan out wafer level semiconductor devices.

3. The method of claim 1 , wherein coupling the integrated routing layer to the number of dies to form the number of fan out batch process carrier level semiconductor devices comprises encapsulating the pillars in an encapsulant.

4. The method of claim 3 , wherein coupling the integrated routing layer to the number of dies to form the number of fan out batch process carrier level semiconductor devices comprises thinning the encapsulant to reveal a top surface of the pillars.

5. The method of claim 1 , wherein coupling the integrated routing layer to the number of dies to form the number of fan out batch process carrier level semiconductor devices comprises plating conductor routes directly onto the pillars.

6. The method of claim 5 , wherein coupling the integrated routing layer to the number of dies to form the number of fan out batch process carrier level semiconductor devices comprises spin coating a dielectric over the conductor routes.

7. A method, comprising:
coupling a number of dies to a batch process carrier in a fan out arrangement, the number of dies arranged with an active surface facing up from the batch process carrier;
coupling an integrated routing layer to the active surface of the number of dies while attached to the batch process carrier, the integrated routing layer extending to a first width with respect to each die in the number of dies;
singulating the number of dies from the fan out batch process carrier at the first width;
testing each singulated die for functionality;
coupling a molded routing layer to functional singulated dies, wherein the molded routing layer extends to a second width wider than the first width; and
encapsulating the functional singulated dies to a width that extends laterally to the same width as the molded routing layer.

8. The method of claim 7 , wherein coupling the molded routing layer to the functional singulated dies comprises soldering the molded routing layer to the functional singulated dies.

9. The method of claim 7 , further comprising exposing a backside of the functional singulated dies.

10. The method of claim 9 , wherein exposing the backside of the functional singulated dies comprises removing the fan out batch process carrier.

11. The method of claim 7 , wherein coupling the integrated routing layer to the active surface of the number of dies comprises encapsulating pillars on the active surface of the number of dies in an encapsulant.

12. The method of claim 11 , wherein coupling the integrated routing layer to the active surface of the number of dies comprises thinning the encapsulant to reveal a top surface of the pillars.

13. The method of claim 11 , wherein coupling the integrated routing layer to the active surface of the number of dies comprises plating conductor routes directly onto a top surface of the pillars.

14. The method of claim 13 , wherein coupling the integrated routing layer to the active surface of the number of dies comprises spin coating a dielectric over the conductor routes.

15. A method, comprising:
coupling a number of dies to a batch process carrier in a fan out arrangement, the number of dies arranged with an active surface facing up from the batch process carrier;
coupling an integrated routing layer to the active surface of the number of dies while attached to the batch process carrier, the integrated routing layer extending to a first width with respect to each die in the number of dies;
singulating the number of dies from the fan out batch process carrier at the first width;
testing each singulated die for functionality;
exposing a backside of functional singulated dies; and
coupling a molded routing layer to the functional singulated dies, wherein the molded routing layer extends to a second width wider than the first width.

16. The method of claim 15 , wherein coupling the molded routing layer to the functional singulated dies comprises soldering the molded routing layer to the functional singulated dies.

17. The method of claim 15 , wherein coupling the integrated routing layer to the active surface of the number of dies comprises encapsulating pillars on the active surface of the number of dies in an encapsulant.

18. The method of claim 17 , wherein coupling the integrated routing layer to the active surface of the number of dies comprises thinning the encapsulant to reveal a top surface of the pillars.

19. The method of claim 17 , wherein coupling the integrated routing layer to the active surface of the number of dies comprises plating conductor routes directly onto a top surface of the pillars.

20. The method of claim 19 , wherein coupling the integrated routing layer to the active surface of the number of dies comprises spin coating a dielectric over the conductor routes.

Assignees

• Intel Corp

Inventors

• Keser Lizabeth
• Ort Thomas
• Wagner Thomas
• Waidhas Bernd

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title