Interfacing with superconducting circuitry

Patent metadata

Field	Value
Publication number	US-12048256-B2
Application number	US-202117241688-A
Country	US
Kind code	B2
Filing date	Apr 27, 2021
Priority date	Apr 27, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

Embodiments of the present disclosure include techniques for interfacing with superconducting circuits and systems. In one embodiment, the present disclosure includes interface circuitry, including driver circuits and/or receiver circuits to send/receive signals with a superconducting circuit. In another embodiment, the present disclosure includes superconducting circuits and techniques for generating a trigger signal from and external clock that is based on a superconducting resonator. In yet another embodiment, the present disclosure includes superconducting data capture circuits that may be used to couple external data to and/or from superconducting logic.

First claim

What is claimed is:

1. A superconducting circuit comprising:
a superconducting logic circuit; and
a plurality of superconducting data capture circuits configured in series, the superconducting data capture circuits storing data represented as pulses,
wherein a first portion of the superconducting data capture circuits have outputs coupled to inputs of the superconducting logic circuit and a second portion of the superconducting data capture circuits have inputs coupled to outputs of the superconducting logic circuit, and
wherein in a first mode the superconducting data capture circuits shift in data to test the superconducting logic circuit, and
wherein in a second mode the superconducting data capture circuits shift out data from outputs of the superconducting logic circuit.

2. The superconducting circuit of claim 1 , wherein the plurality of superconducting data capture circuits are coupled to an RQL clock signal to synchronously shift data in and out of the plurality of superconducting data capture circuits configured in series.

3. The superconducting circuit of claim 2 , further comprising a superconducting resonator, wherein the RQL clock signal is generated from transitions of an external clock having a lower frequency than a frequency of the superconducting resonator, and wherein a logical pulse width of the RQL clock signal is equal to the logical pulse width of the superconducting resonator.

4. The superconducting circuit of claim 3 , wherein the data is shifted in at a first frequency corresponding to the external clock in a first mode, and wherein the data is processed by the superconducting logic circuit at a second frequency of the superconducting resonator in a second mode.

5. The superconducting circuit of claim 1 , wherein a first superconducting data capture circuit in the series of superconducting data capture circuits is configured to receive digital bits to test the superconducting logic circuit, and a last superconducting data capture circuit in the series of superconducting data capture circuits is configured to send digital bits produced by the superconducting logic circuit.

6. The superconducting circuit of claim 1 , the plurality of superconducting data capture circuits comprising:
a first multiplexer comprising a first input configured to receive a serial data input from an upstream superconducting data capture circuit, a second input, a select input, and an output;
a second multiplexer comprising a first input coupled to the output of the first multiplexer, a second input, a select input, and an output; and
a delay circuit comprising an input coupled to the output of the second multiplexer and an output coupled to the second input of the multiplexer to store data received at the first or second inputs of the second multiplexer.

7. The superconducting circuit of claim 6 , wherein the second input of the first multiplexer is coupled to an output of the superconducting logic circuit, wherein a first signal coupled to the select input of the first multiplexer shifts data into the plurality of superconducting data capture circuits in a first mode and the first signal couples data from the superconducting logic circuit to the second input of the second multiplexer in a second mode.

8. The superconducting circuit of claim 6 , wherein the output of the delay circuit is coupled to an input of the superconducting logic circuit.

9. A superconducting interface circuit comprising:
a single-ended to differential driver configure to receive a digital clock signal;
a differential attenuator coupled to a differential output of the single-ended to differential driver;
a reciprocal quantum logic (RQL) receiver circuit coupled to an output of the differential attenuator to convert the digital clock signal to an RQL clock signal;
an RQL transition detection circuit configured to receive the RQL clock signal and generate one or more RQL logic pulse signals corresponding to logic transitions of the digital clock signal, the RQL logic pulse signals having a logical pulse width equal to a logical pulse width of a superconducting resonator circuit; and
a plurality of RQL multiplexers configured between a plurality of superconducting logic circuits to send and receive test data to and from the superconducting logic circuits during a test mode of operation, wherein at least a portion of the plurality of RQL multiplexers store data represented as pulses.

10. The superconducting interface circuit of claim 9 , wherein the differential attenuator comprises a plurality of resistors configured in 2-port differential series-parallel network.

11. The superconducting interface circuit of claim 9 , wherein the RQL transition detection circuit comprises:
an RQL delay circuit having an input coupled to receive the RQL clock signal;
a first RQL inverter coupled to an output of the first delay circuit; and
a first RQL AND circuit having a first input coupled to the input of the RQL delay circuit and a second input coupled to an output of the first RQL inverter.

12. The superconducting interface circuit of claim 11 , wherein the RQL delay circuit has a time delay equal to a cycle of the superconducting resonator circuit.

13. The superconducting interface circuit of claim 11 , wherein an output of the first RQL AND circuit is an RQL logic pulse signal corresponding to a rising transition of the digital clock signal and having a logical pulse width equal to a logical pulse width of a superconducting resonator circuit.

14. The superconducting interface circuit of claim 11 , wherein the RQL transition detection circuit further comprises:
a second RQL inverter coupled to the input of the RQL delay circuit; and
a second RQL AND circuit having a first input coupled to the output of the RQL delay circuit and a second input coupled to an output of the second RQL inverter.

15. The superconducting interface circuit of claim 14 , wherein an output of the second RQL AND circuit is an RQL logic pulse signal corresponding to a falling transition of the digital clock signal and having a logical pulse width equal to a logical pulse width of a superconducting resonator circuit.

16. The superconducting interface circuit of claim 9 , further comprising:
an RQL driver circuit configured to receive data from at least one of the RQL multiplexers and produce a differential signal on a differential output;
an AC coupling circuit having a differential input coupled to the differential output of the RQL driver circuit;
an amplification stage having a differential input coupled to a differential output of the AC coupling circuit;
a comparator circuit having a differential input coupled to a differential output of the amplification stage; and
a flip flop configured to store logical data values received from the RQL driver circuit.

17. A superconducting circuit comprising:
a superconducting logic circuit;
a superconducting resonator circuit having a first frequency;
an RQL transition detection circuit configured to receive an external clock signal having a second frequency less than the first frequency and generate one or more RQL logic pulse signals corresponding to logic transitions of the external clock signal, the RQL logic pulse signals having a logical pulse width equal to a logical pulse width of the superconducting resonator circuit; and
a plurality of series coupled superconducting data capture circuits configured to shift data to and from an external data source synchronously with the superconducting resonator circuit based on at least one of the RQL logic pulse signals, the supercond

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Comparan Miguel
• Muff Adam James
• Sen Indranil
• Berndt Paul D

Classifications

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• H10N60/84 Primary

  Switching means for devices switchable between superconducting and normal states · CPC title

• H03K19/195 Primary

  using superconductive devices · CPC title