Reciprocal Quantum Logic (RQL) circuit synthesis

Patent metadata

Field	Value
Publication number	US-9652571-B2
Application number	US-201414526904-A
Country	US
Kind code	B2
Filing date	Oct 29, 2014
Priority date	Oct 29, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.

First claim

What is claimed is:

1. A non-transitory computer readable medium configured to store instructions that, when executed, are configured to perform a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool, the method comprising:
providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool;
generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and the component library;
separating the circuit system into a plurality of circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs;
removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool based on the inputs to generate the RQL circuit design from the RQL netlist circuit; and
controlling fabrication of a semiconductor circuit based on the generated RQL circuit design.

2. The medium of claim 1 , further comprising replacing the flip-flop device placeholder in the RQL netlist circuit with a plurality of sequential flip-flop devices controlled by a separate clock signal corresponding respectively to each separate phase of the clock signal.

3. The medium of claim 2 , wherein separating the circuit system comprises performing a register rebalance operation on the RQL netlist circuit via the synthesis tool to separate the circuit system into the plurality of circuit subsystems that are each associated with a separate one of the plurality of sequential flip-flop devices, such that each of the plurality of sequential flip-flops interconnect a respective pair of the plurality of circuit subsystems.

4. The medium of claim 3 , wherein removing the flip-flop device placeholder comprises:
removing each of the plurality of sequential flip-flops to provide a coupling of each respective pair of the plurality of circuit subsystems with respect to each other; and
associating each separate phase of the clock signal to a respective one of the plurality of circuit subsystems to provide sequential triggering of the plurality of circuit subsystems at each separate respective phase of the clock signal via the inputs.

5. The medium of claim 3 , further comprising:
evaluating clock phases associated with each of the plurality of circuit subsystems; and
adding at least one Josephson transmission line (JTL) via the inputs to a substantially empty one of the plurality of circuit subsystems that would result in conductive coupling of a pair of the plurality of circuit subsystems having non-consecutive clock phases in response to removal of the plurality of sequential flip-flops.

6. The medium of claim 1 , wherein separating the circuit system comprises performing a register rebalance operation on the RQL netlist circuit via the synthesis tool to separate the circuit system into the plurality of circuit subsystems that are each associated with the separate respective phase of the clock signal.

7. The medium of claim 6 , wherein providing the inputs comprises replacing the flip-flop device placeholder with a plurality of sequential flip-flop devices that are each associated with a respective one of the plurality of circuit subsystems and are each controlled by a separate clock signal corresponding respectively to each separate respective phase of the clock signal.

8. The medium of claim 1 , further comprising:
evaluating clock phases associated with each of the plurality of circuit subsystems; and
adding at least one Josephson transmission line (JTL) via the inputs to a substantially empty one of the plurality of circuit subsystems that would result in conductive coupling of a pair of the plurality of circuit subsystems having non-consecutive clock phases.

9. The medium of claim 8 , wherein evaluating the clock phases comprises evaluating each conductive coupling between each of the plurality of circuit subsystems, and wherein adding the at least one JTL comprises adding one JTL for each phase-segment difference of the phase of the clock signal greater than one between the given conductively-coupled pair of the plurality of circuit subsystems.

10. The medium of claim 1 , wherein the clock signal is a quadrature clock signal comprising four phases, such that the plurality of circuit subsystems comprises a first circuit subsystem, a second circuit subsystem, a third circuit subsystem, and a fourth circuit subsystem.

11. The medium of claim 1 , wherein the synthesis tool is a complementary metal-oxide semiconductor (CMOS) circuit synthesis tool.

12. A non-transitory computer readable medium configured to store instructions that, when executed, are configured to perform a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a CMOS synthesis tool, the method comprising:
providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool;
generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and the component library;
replacing the flip-flop device placeholder with a plurality of sequential flip-flop devices controlled by a separate clock signal corresponding respectively to each separate phase of the clock signal based on inputs;
separating the circuit system into a plurality of circuit subsystems that are each associated with a separate one of the plurality of sequential flip-flop devices, such that each of the plurality of sequential flip-flops interconnect a respective pair of the plurality of circuit subsystems based on the inputs;
removing each of the plurality of sequential flip-flop devices from the RQL netlist circuit via the synthesis tool based on the inputs to generate the RQL circuit design based on the RQL netlist circuit; and
controlling fabrication of a semiconductor circuit based on the generated RQL circuit design.

13. The medium of claim 12 , wherein separating the circuit system comprises performing a register rebalance operation on the RQL netlist circuit via the synthesis tool to separate the circuit system into the plurality of circuit subsystems that are each associated with the separate one of the plurality of sequential flip-flop devices.

14. The medium of claim 12 , wherein removing each of the plurality of sequential flip-flops comprises:
providing a coupling of each respective pair of the plurality of circuit subsystems with respect to each other; and
associating each separate phase of the clock signal to a respective one of the plurality of circuit subsystems to provide sequential triggering of the plurality of circuit subsystems at each separate respective phase of the clock signal via the inputs.

15. The medium of claim 12 , further comprising:
evaluating clock phases associated with each of the plurality of circuit subsystems prior to removing each of the plurality of sequential flip-flop devices; and
adding at least one Josephson transmission line (JTL) via the inputs to a substantially empty one of the plurality of circuit subsystems that would result in conductive coupling of a pair of the plurality of circuit subsystems having non-consecutive clock phases in response to removal of the plurality of sequential flip-flops.

16. The medium of claim 12 , wherein the clock signal is a quadrature clock signal comprising fo

Assignees

• Shauck Steven B
• Phifer Gary L
• Northrop Grumman Systems Corp

Inventors

• Shauck Steven B
• Phifer Gary L

Classifications

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/3312

  Timing analysis · CPC title