Phase-mode based superconducting logic

Patent metadata

Field	Value
Publication number	US-9543959-B1
Application number	US-201514919588-A
Country	US
Kind code	B1
Filing date	Oct 21, 2015
Priority date	Oct 21, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.

First claim

What is claimed:

1. A device comprising:
a plurality of Josephson junctions;
at least one terminal for receiving an input signal;
at least one clock terminal for receiving a return-to-zero clock signal;
at least one latch;
at least one logic gate comprising at least a subset of the plurality of Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch;
at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch; and
at least one output terminal for providing an output of the at least one latch by processing the first signal and the second signal.

2. The device of claim 1 , wherein the at least one latch is a set-reset latch.

3. The device of claim 2 , wherein the first signal is configured to set the set-reset latch and wherein the second signal is configured to reset the set-reset latch.

4. The device of claim 1 , wherein the at least one latch is a D-latch.

5. The device of claim 1 , wherein the at least one phase-mode logic inverter comprises a flip gate coupled to: (1) a mirrored Josephson transmission line and (2) a DC-flux bias circuit.

6. The device of claim 5 , wherein the at least one phase-mode logic inverter is configured to change a phase of the return-to-zero clock signal from a low phase to a high phase or from a high phase to a low phase.

7. The device of claim 1 , wherein the output of the at least one latch is encoded as a phase-mode signal such that a logic high corresponds to a high phase of the phase-mode signal and a logic low corresponds to a low phase of the phase-mode signal.

8. A method in a device comprising: (1) a plurality of Josephson junctions, (2) at least one latch, and (3) a plurality of logic gates comprising at least a subset of the plurality of Josephson junctions, the method comprising:
receiving a return-to-zero clock signal;
receiving an input signal;
using the plurality of logic gates, processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch;
using at least a phase-mode logic inverter, processing the return-to-zero clock signal to generate a second signal for the at least one latch; and
based on at least the first signal and the second signal, providing an output of the at least one latch.

9. The method of claim 8 , wherein the at least one latch is a set-reset latch.

10. The method of claim 8 , wherein the first signal is configured to set the set-reset latch and wherein the second signal is configured to reset the set-reset latch.

11. The method of claim 8 , wherein the at least one latch is a D-latch.

12. The method of claim 8 , wherein the at least one phase-mode logic inverter comprises a flip gate coupled to: (1) a mirrored Josephson transmission line and (2) a DC-flux bias circuit.

13. The method of claim 8 further comprising, using the at least one phase-mode logic inverter, changing a phase of the return-to-zero clock signal from a low phase to a high phase or from a high phase to a low phase.

14. The method of claim 8 , wherein the output of the at least one latch is encoded as a phase-mode signal such that a logic high corresponds to a high phase of the phase-mode signal and a logic low corresponds to a low phase of the phase-mode signal.

15. A device comprising:
a plurality of Josephson junctions;
at least one terminal for receiving an input signal;
at least one clock terminal for receiving a return-to-zero clock signal;
at least one latch;
at least one logic gate, comprising at least a subset of the plurality of Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch;
at least one inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch; and
at least one output terminal for providing an output of the at least one latch by processing the first signal and the second signal, wherein the output of the at least one latch is persistent across at least four phases of a sinusoidal clock signal.

16. The device of claim 15 , wherein the at least one latch is a set-reset latch.

17. The device of claim 16 , wherein the first signal is configured to set the set-reset latch and wherein the second signal is configured to reset the set-reset latch.

18. The device of claim 15 , wherein the at least one latch is a D-latch.

19. The device of claim 15 , wherein the at least one inverter comprises a flip gate coupled to: (1) a mirrored Josephson transmission line and (2) a DC-flux bias circuit.

20. The device of claim 15 , wherein the at least one inverter is configured to change a phase of the return-to-zero clock signal from a low phase to a high phase or from a high phase to a low phase.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Carmean Douglas
• Braun Alexander
• Herr Anna Y
• Herr Quentin P

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• H03K19/0008

  Arrangements for reducing power consumption · CPC title

• H03K19/195 Primary

  using superconductive devices · CPC title