Superconducting non-destructive readout circuits

Patent metadata

Field	Value
Publication number	US-10554207-B1
Application number	US-201816051058-A
Country	US
Kind code	B1
Filing date	Jul 31, 2018
Priority date	Jul 31, 2018
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

First claim

What is claimed is:

1. A reciprocal quantum logic (RQL) non-destructive readout (NDRO) gate comprising:
a body circuit having at least one single flux quantum (SFQ) logical input, the body circuit being configured to store at least one logical state; and
at least one tail circuit connected to the body circuit, the at least one tail circuit comprising:
a tail input inductor connected between an NDRO read-enable input port and the body circuit and configured to receive an SFQ pulse NDRO read-enable signal on the NDRO read-enable input port;
a tail Josephson junction connected between the body circuit and a circuit ground; and
a tail output inductor connected between the body circuit and an NDRO output port and configured to transmit an SFQ pulse NDRO output signal based on the stored logical state and the NDRO read-enable signal without affecting the stored logical state.

2. The NDRO gate of claim 1 , wherein the at least one tail circuit is configured to receive the logical state from the body circuit as a pre-critical state bias current that biases the tail Josephson junction to trigger upon receipt of the NDRO read-enable signal and thereby to propagate the NDRO output signal to the NDRO output port.

3. The NDRO gate of claim 1 , wherein the at least one tail circuit comprises no more than one Josephson junction and no more than two inductors, exclusive of any output Josephson transmission line (JTL) connected to the tail output inductor.

4. The NDRO gate of claim 1 , comprising exactly two tail circuits providing exactly two NDRO read-enable input ports and exactly two NDRO output ports, the tail circuits being configured to respectively transmit an SFQ pulse NDRO output signal based on the same stored logical state but on different respective NDRO read-enable signals provided from the respective NDRO read-enable input ports.

5. A register file comprising an array of multiple instances of the NDRO gate of claim 4 .

6. The NDRO gate of claim 1 , wherein the body circuit comprises a D latch having a data input port and a logical clock input port each configured to receive SFQ pulses.

7. The NDRO gate of claim 6 , wherein the D latch comprises:
a data input inductor connected between the data input port and a first node;
a data input Josephson junction connected between the first node and the circuit ground;
a state storage Josephson junction connected between a second node and the circuit ground;
a first DC flux bias transformer connected between a third node and the first node and to a DC flux bias line;
a second DC flux bias transformer connected between the second node and the third node and to the DC flux bias line;
a logical clock input inductor connected between the logical clock input port and a fourth node;
an escape Josephson junction connected between the fourth node and the second node; and
at least one linking inductor connected between the third node and the at least one tail circuit,
wherein the first and second DC flux bias transformers are configured to provide at an initialization time a fraction of a Φ 0 of phase to the data input Josephson junction and the state storage Josephson junction.

8. The NDRO gate of claim 7 , wherein the D latch comprises at least two linking inductors connected between the third node and respective at least two tail circuits.

9. The NDRO gate of claim 6 , wherein the D latch comprises:
a data input inductor connected between the data input port and a first node;
a data input Josephson junction connected between the first node and the circuit ground;
a state storage Josephson junction connected between a second node and the circuit ground;
only a single DC flux bias transformer connected between the second node and the first node and to a DC flux bias line;
a logical clock input inductor connected between the logical clock input port and a fourth node;
an escape Josephson junction connected between the fourth node and the second node;
a first linking inductor connected between the first node and the at least one tail circuit; and
a second linking inductor connected between the second node and the at least one tail circuit,
wherein the single DC flux bias transformer is configured to provide at an initialization time a fraction of a Φ 0 of phase to the data input Josephson junction and the state storage Josephson junction.

10. The NDRO gate of claim 9 , wherein the gate comprises at least two tail circuits, and wherein the D latch further comprises:
a third linking inductor connected between the first node and a second tail circuit; and
a fourth linking inductor connected between the second node and the second tail circuit.

11. The NDRO gate of claim 1 , wherein the body circuit comprises a D flip-flop having a data input port and a logical clock input port each configured to receive SFQ pulses.

12. The NDRO gate of claim 11 , wherein the D flip-flop comprises:
a data input inductor connected between the data input port and a first node;
a data input Josephson junction connected between the first node and the circuit ground;
a state storage Josephson junction connected between a second node and the circuit ground;
a first inductor connected between a third node and the first node;
a second inductor connected between the second node and the third node;
a logical clock input inductor connected between the logical clock input port and a fourth node;
an escape Josephson junction connected between the fourth node and the second node; and
at least one linking inductor connected between the third node and the at least one tail circuit,
wherein the D flip-flop does not include a DC flux bias transformer connected to a DC flux bias line.

13. The NDRO gate of claim 1 , configured as a multiplexer, comprising exactly two tail circuits having their respective output ports both connected to a single output, and wherein the body circuit comprises a pulse generator comprising two Josephson junctions and an AC bias source, and wherein a logical input to the body provides a selector signal that selects between:
a signal arriving on an input port of a first of the two tail circuits being propagated to the single output, or
a signal arriving on an input port of a second of the two tail circuits being propagated to the single output.

14. The NDRO gate of claim 1 , configured as an AND-OR gate, comprising exactly two tail circuits having their respective output ports both connected to a single output, and wherein the body circuit comprises two logical inputs configured such that:
an assertion of a first of the two logical inputs permits a signal arriving on an input port of a first of the two tail circuits to be propagated to the single output, and
an assertion of a second of the two logical inputs permits a signal arriving on an input port of a second of the two tail circuits to be propagated to the single output.

15. The NDRO gate of claim 1 , configured as an AND gate, the gate having only a single tail circuit, and wherein the body circuit consists solely of:
a logical input inductor connected between a logical input port and a first node;
a state relay Josephson junction connected between the first node and the circuit ground; and
a linking inductor connected between the first node and the single tail circuit,
wherein the tail circuit outputs a signal representing a logical AND of the NDRO read-enable signal and a body input signal provided at the logical input port of the body circuit.

16. The NDRO gate of claim 1 , configured as an A-NOT-B gate, the gate having only a single tail circuit, and wherein t

Assignees

• Herr Anna Y
• Herr Quentin P
• Clarke Ryan Edward
• Hearne Iii Harold Clifton
• Braun Alexander Louis
• Burnett Randall M
• Lee Timothy Chi Chao
• Northrop Grumman Systems Corp

Inventors

• Herr Anna Y
• Herr Quentin P
• Clarke Ryan Edward
• Hearne Iii Harold Clifton
• Braun Alexander Louis
• Burnett Randall M
• Lee Timothy Chi-Chao

Classifications

• H03K19/195 Primary

  using superconductive devices · CPC title

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G11C11/44 Primary

  using super-conductive elements, e.g. cryotron · CPC title

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title