Methods of fabricating semiconductor package

Patent metadata

Field	Value
Publication number	US-12046526-B2
Application number	US-202217735471-A
Country	US
Kind code	B2
Filing date	May 3, 2022
Priority date	Aug 30, 2019
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.

First claim

What is claimed is:

1. A semiconductor package comprising:
an insulating layer;
a redistribution layer including a first portion and a second portion on the first portion;
a solder ball directly contacting the first portion of the redistribution layer and the insulating layer; and
a semiconductor chip on a top surface of the insulating layer,
wherein a bottom surface of the first portion of the redistribution layer is above a bottom surface of the insulating layer,
a first height from the bottom surface of the insulating layer to the first portion of the redistribution layer is less than a second height from the bottom surface of the insulating layer to the second portion of the redistribution layer,
a width of the first portion of the redistribution layer is less than a width of the second portion of the redistribution layer, and
a top surface of the redistribution layer is coplanar with the top surface of the insulating layer.

2. The semiconductor package of claim 1 , wherein the bottom surface of the first portion is disposed in the insulating layer.

3. The semiconductor package of claim 1 , wherein the redistribution layer includes copper.

4. The semiconductor package of claim 1 , wherein the insulating layer includes a photo-imageable dielectric material.

5. The semiconductor package of claim 1 , further comprising:
a molding part covering at least a portion of the semiconductor chip on the top surface of the insulating layer.

6. The semiconductor package of claim 5 , wherein a top surface of the molding part is coplanar with a top surface of the semiconductor chip.

7. A semiconductor package comprising:
a redistribution layer including an electrode pad and a sub-redistribution layer on the electrode pad;
an insulating layer on a side surface of the redistribution layer and including a trench on at least a portion of the electrode pad;
a solder ball in the trench and directly contacting the electrode pad and the insulating layer; and
a semiconductor chip on the redistribution layer, wherein a bottom surface of the electrode pad faces the solder ball, and the solder ball has a width that is the same as a width of the bottom surface of the electrode pad;
wherein the electrode pad and the sub-redistribution layer have an integral structure, and a top surface of the redistribution layer is coplanar with a top surface of the insulating layer;
wherein each of the electrode pad and the sub-redistribution layer extend along a first direction; and
wherein a first width of the electrode pad is less than a second width of the sub-redistribution layer.

8. The semiconductor package of claim 7 , wherein the electrode pad is on a portion of the sub-redistribution layer with the first width.

9. The semiconductor package of claim 7 , wherein the first width increases from the solder ball to the sub-redistribution layer.

10. The semiconductor package of claim 7 , wherein a first height from a bottom surface of the insulating layer to the electrode pad is less than a second height from the bottom surface of the insulating layer to the sub-redistribution layer.

11. The semiconductor package of claim 7 , wherein the electrode pad entirely overlaps the sub-redistribution layer.

12. A semiconductor package comprising:
a redistribution structure including a first insulating layer, a first redistribution layer in the first insulating layer, a second insulating layer on the first insulating layer, and a second redistribution layer electrically connected to the first redistribution layer in the second insulating layer, wherein each of the first redistribution layer and second redistribution layer includes a first portion having a first width and a second portion having a second width greater than the first width on the first portion;
a semiconductor chip on the redistribution structure;
a bump between the redistribution structure and the semiconductor chip;
a solder ball contacting the first insulating layer and the first portion of the first redistribution layer; and
a molding part covering at least a portion of the semiconductor chip on the redistribution structure,
wherein a first height from a bottom surface of the first insulating layer to the first portion of the first redistribution layer is less than a second height from the bottom surface of the first insulating layer to the second portion of the first redistribution layer, a width of the first portion of the first redistribution layer is less than a width of the second portion of the first redistribution layer, and a top surface of the first redistribution layer is coplanar with a top surface of the first insulating layer.

13. The semiconductor package of claim 12 , wherein the first redistribution layer includes a same material as the second redistribution layer.

14. The semiconductor package of claim 12 , wherein the first insulating layer includes a same material as the second insulating layer.

15. The semiconductor package of claim 12 , wherein a top surface of the molding part is coplanar with a top surface of the semiconductor chip.

16. The semiconductor package of claim 12 , wherein the first width of each of the first and the second redistribution layers increases from a bottom surface of the redistribution structure to a top surface of the redistribution structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jung-Ho
• Park Jin-Woo
• Jang Jae Gwon
• Jeon Gwang Jae

Classifications

• H10P72/7448

  the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/07236

  Soldering or alloying · CPC title