Structure and formation method of chip package with fan-out structure

Patent metadata

Field	Value
Publication number	US-10276536-B2
Application number	US-201715499962-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Apr 28, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.

First claim

What is claimed is:

1. A method for forming a chip package, comprising:
forming a protective layer to surround a semiconductor die, wherein the protective layer has opposing first and second surfaces;
forming a dielectric layer over the first surface of the protective layer and the semiconductor die;
forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die;
disposing a polymer-containing material to partially cover the second surface of the protective layer; and
curing the polymer-containing material to form a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.

2. The method for forming a chip package as claimed in claim 1 , further comprising:
disposing a mold over the semiconductor die;
injecting a molding compound material into the mold to surround the semiconductor die;
curing the molding compound material to form the protective layer; and
removing the mold.

3. The method for forming a chip package as claimed in claim 1 , further comprising forming a conductive bump over the second surface of the protective layer, wherein the conductive bump is electrically connected to a second conductive element of the semiconductor die, and the warpage-control element is not in direct contact with the conductive bump.

4. The method for forming a chip package as claimed in claim 1 , further comprising:
forming a conductive pillar beside the semiconductor die before the protective layer is formed;
placing a stencil over the second surface of the protective layer to cover the conductive pillar;
printing a polymer-containing material over the protective layer through openings of the stencil; and
curing the polymer-containing material to form the warpage-control element.

5. The method for forming a chip package as claimed in claim 4 , further comprising forming a conductive bump on the conductive pillar after the warpage-control element is formed.

6. The method for forming a chip package as claimed in claim 1 , further comprising forming a conductive bump over the second surface of the protective layer.

7. The method for forming a chip package as claimed in claim 6 , wherein the conductive bump is formed before the warpage-control element is formed.

8. The method for forming a chip package as claimed in claim 7 , further comprising:
placing a stencil over the second surface of the protective layer to cover the conductive bump;
printing a polymer-containing material over the protective layer through openings of the stencil; and
curing the polymer-containing material to form the warpage-control element.

9. The method for forming a chip package as claimed in claim 7 , further comprising:
placing a stencil over the second surface of the protective layer to partially cover the conductive bump;
printing a polymer-containing material over the protective layer through openings of the stencil; and
curing the polymer-containing material to form the warpage-control element, wherein the warpage-control element is in direct contact with the conductive bump.

10. A method for forming a chip package, comprising:
forming a plurality of conductive pillars and disposing a plurality of semiconductor dies over a carrier substrate;
forming a protective layer over the carrier substrate to surround the conductive pillars and the semiconductor dies;
forming a dielectric layer over the protective layer, the conductive pillars, and the semiconductor dies;
forming a plurality of first conductive bumps over the dielectric layer;
removing the carrier substrate;
forming a plurality of second conductive bumps over the protective layer, wherein the first conductive bumps and the second conductive bumps are positioned over opposite sides of the protective layer; and
forming a plurality of warpage-control elements over the protective layer.

11. The method for forming a chip package as claimed in claim 10 , further comprising performing a cutting operation to the protective layer to form a plurality of chip packages, wherein one of the chip packages comprises one of the semiconductor dies and one of the warpage-control elements.

12. The method for forming a chip package as claimed in claim 10 , wherein the second conductive bumps are formed before the warpage-control elements are printed.

13. The method for forming a chip package as claimed in claim 10 , further comprising:
disposing a mold over the carrier substrate to surround a space;
injecting a molding compound material into the space to surround the semiconductor dies and the conductive pillars;
curing the molding compound material to form the protective layer; and
removing the mold.

14. The method for forming a chip package as claimed in claim 10 , further comprising forming a base layer over the carrier substrate before the conductive pillars are formed, wherein the base layer has a greater light transmittance than that of each of the warpage-control elements.

15. The method for forming a chip package as claimed in claim 14 , further comprising forming a plurality of openings in the base layer to expose the conductive pillars after the carrier substrate is removed, wherein the second conductive bumps fill the openings.

16. A chip package, comprising:
a semiconductor die;
a protective layer surrounding the semiconductor die;
a conductive pillar penetrating through opposite surfaces of the protective layer and separated from the semiconductor die by the protective layer; and
a conductive bump and a warpage-control element over a same side of the protective layer, wherein the conductive bump is electrically connected to the conductive pillar, and the warpage-control element is separated from the conductive bump, a top surface of the warpage-control element is higher than a bottom surface of the conductive bump, and the top surface of the warpage-control element is lower than a top surface of the conductive bump.

17. The chip package as claimed in claim 16 , further comprising a base layer over the protective layer, wherein the base layer surrounds a portion of the conductive bump, and the base layer is between the warpage-control element and the semiconductor die.

18. The chip package as claimed in claim 17 , wherein the base layer has a greater light transmittance than that of the warpage-control element.

19. The chip package as claimed in claim 17 , wherein the warpage-control element has a greater area than that of the semiconductor die.

20. The chip package as claimed in claim 16 , further comprising a second semiconductor die stacked over the semiconductor die, wherein the warpage control element is between the semiconductor die and the second semiconductor die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pei Hao-Jan
• Tsao Chih-Chiang
• Chen Wei-Yu
• Lin Hsiu-Jen
• Cheng Ming-Da
• Hsieh Ching-Hua
• Liu Chung-Shi

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title