Floating-point dynamic range expansion

Patent metadata

Field	Value
Publication number	US-12045581-B2
Application number	US-202217711857-A
Country	US
Kind code	B2
Filing date	Apr 1, 2022
Priority date	Sep 27, 2018
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

The present disclosure relates generally to techniques for adjusting the number representation (e.g., format) of a variable before and/or after performing one or more arithmetic operations on the variable. In particular, the present disclosure relates to scaling the range of a variable to a suitable representation based on available hardware (e.g., hard logic) in an integrated circuit device. For example, an input in a first number format (e.g., bfloat16) may be scaled to a second number format (e.g., half-precision floating-point) so that circuitry implemented to receive inputs in the second number format may perform one or more arithmetic operations on the input. Further, the output produced by the circuitry may be scaled back to the first number format. Accordingly, arithmetic operations, such as a dot-product, performed in a first format may be emulated by scaling the inputs to and/or the outputs from arithmetic operations performed in another format.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
first scaling circuitry configurable to receive a first set of inputs having a first range and generate a first set of scaled inputs by scaling a respective exponent of each input of the first set of inputs from the first range to a second range;
first arithmetic circuitry communicatively coupled to the first scaling circuitry and configurable to perform one or more arithmetic operations on the first set of scaled inputs and to produce an output; and
second scaling circuitry communicatively coupled to the first arithmetic circuitry and configurable to produce a scaled output by scaling the output to have the first range.

2. The integrated circuit device of claim 1 , wherein the second range is less than the first range.

3. The integrated circuit device of claim 2 , wherein the output has a third range.

4. The integrated circuit device of claim 3 , wherein the third range is greater than the first range.

5. The integrated circuit device of claim 1 , comprising a digital signal processing (DSP) block, wherein the DSP block comprises the first arithmetic circuitry.

6. The integrated circuit device of claim 5 , comprising programmable logic.

7. The integrated circuit device of claim 6 , wherein the integrated circuit device is a field-programmable gate array.

8. The integrated circuit device of claim 1 , wherein the first scaling circuitry is configurable to scale the respective exponent of each of the first set of inputs by:
determining a first set of exponent sums by summing, for each pair of inputs of the first set of inputs, a first exponent of a respective first input of the respective pair and a second exponent of a respective second input of the respective pair; and
scaling the respective exponent of each of the first set of inputs from the first range to the second range based at least in part on a maximum exponent sum of the first set of exponent sums.

9. The integrated circuit device of claim 2 , wherein the first arithmetic circuitry comprises a multiplier.

10. The integrated circuit device of claim 1 , wherein the one or more arithmetic operations comprises a dot-product.

11. The integrated circuit device of claim 1 , wherein each input of the first set of inputs comprises sixteen bits.

12. The integrated circuit device of claim 11 , wherein the output comprises thirty-two bits.

13. A digital signal processing (DSP) block comprising:
input circuitry communicatively coupled to first scaling circuitry, wherein the input circuitry is configured to receive, from the first scaling circuitry, a first set of scaled inputs generated by the first scaling circuitry by scaling a respective exponent of each value of a first set of values from a first number of exponent bits to a second number of exponent bits;
first arithmetic circuitry configurable to perform one or more arithmetic operations on the first set of scaled inputs and to produce an output value; and
output circuitry communicatively coupled to second scaling circuitry that is configurable to produce a scaled output by scaling the output value to have the first number of exponent bits.

14. The DSP block of claim 13 , wherein the DSP block is included in an integrated circuit device.

15. The DSP block of claim 14 , wherein the integrated circuit device is a programmable logic device.

16. A system comprising:
a substrate; and
an integrated circuit device mounted on the substrate, the integrated circuit device, comprising:
first scaling circuitry configurable to receive a first set of inputs having a first range and generate a first set of scaled inputs by scaling a respective exponent of each input of the first set of inputs from the first range to a second range;
first arithmetic circuitry communicatively coupled to the first scaling circuitry and configurable to perform one or more arithmetic operations on the first set of scaled inputs and to produce an output; and
second scaling circuitry communicatively coupled to the first arithmetic circuitry and configurable to produce a scaled output by scaling the output to have the first range.

17. The system of claim 16 , comprising a second integrated circuit device mounted on the substrate, memory circuitry mounted on the substrate, storage circuitry mounted on the substrate, or a combination thereof.

18. The system of claim 17 , comprising the second integrated circuit device, wherein:
the integrated circuit device comprises programmable logic; and
the second integrated circuit device is a processor.

19. The system of claim 16 , wherein the first range is a first number of exponent bits, and the second range is a second number of exponent bits that is less than the first number of exponent bits.

20. The system of claim 19 , wherein the second scaling circuitry is configurable to produce the scaled output by converting the output from a first floating-point format to a second floating-point format.

Assignees

• Intel Corp

Inventors

• Pasca Bogdan Mihai
• Langhammer Martin

Classifications

• G06F7/575

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title