Multiple-mask multiple-exposure lithography and masks

Patent metadata

Field	Value
Publication number	US-12044977-B2
Application number	US-202318359447-A
Country	US
Kind code	B2
Filing date	Jul 26, 2023
Priority date	Jul 31, 2017
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

First claim

What is claimed is:

1. A method comprising:
using a first photomask and a second photomask to form an integrated circuit, wherein the first photomask includes:
a first die area that includes a first portion of a first mask feature for forming the integrated circuit;
a first stitching area disposed along an outer boundary of the first die area that includes a second portion of the first mask feature and a first alignment mark for in-chip overlay measurement with respect to the second photomask, the first portion and the second portion of the first mask feature interfacing with each other at the outer boundary of the first die area;
a frame area disposed along the outer boundary of the first die area that includes a second alignment mark for in-chip overlay measurement with respect to the second photomask, and

wherein the second photomask includes:
a second die area; and
a second stitching area that includes a third portion of the first mask feature.

2. The method of claim 1 , wherein the first portion of the first mask feature has a first width and the second portion of the first mask feature has a second width that is different than the first width.

3. The method of claim 1 , wherein the frame area further includes a third alignment mark for interlevel overlay measurement.

4. The method of claim 1 , wherein the first alignment mark included a plurality of alignment marks for in-chip overlay measurement.

5. The method of claim 1 , wherein the second stitching area includes a third alignment mark for in-chip overlay measurement, wherein the first photomask further includes a second stitching area disposed along the outer boundary of the first die area that includes a first portion of a second mask feature and a third alignment mark for in-chip overlay measurement with respect to a third photomask, and
wherein using the first photomask and the second photomask to form the integrated circuit includes using the third photomask.

6. The method of claim 5 , wherein the first photomask further includes a third stitching area between the first and second stitching areas that is free of any mask features for forming the integrated circuit.

7. The method of claim 1 , wherein the first alignment mark has a different shape than the second alignment mark.

8. The method of claim 1 , wherein the first alignment mark is selected from the group consisting of an inner box alignment feature, an outer box alignment feature, an inner cross alignment feature, an outer cross alignment feature, and a test line, and
wherein the second alignment mark is selected from the group consisting of an inner box alignment feature, an outer box alignment feature, an inner cross alignment feature, an outer cross alignment feature, and a test line.

9. A method comprising:
using a first photomask, a second photomask and a third photomask to form an integrated circuit, wherein the first photomask includes:
a first die area that includes a first portion of a mask feature for forming the integrated circuit; and
a first stitching area that includes a second portion of the mask feature and a first alignment mark for in-chip overlay measurement with respect to the second photomask,
a second stitching area that includes a second alignment mark for in-chip overlay measurement with respect to the third photomask

wherein the second photomask includes:
a second die area; and
a third stitching area that includes a third alignment mark for in-chip overlay measurement with respect to the first photomask, and

wherein the third photomask includes:
a third die area; and
a fourth stitching area that includes a fourth alignment mark for in-chip overlay measurement with respect to the first photomask.

10. The method of claim 9 , wherein the third and fourth stitching areas are free of any mask features for forming the integrated circuit.

11. The method of claim 9 , wherein the third stitching area includes a plurality of mask features for forming the integrated circuit.

12. The method of claim 9 , wherein the first photomask further includes a frame area proximate the first die area that includes a fifth alignment mark for interlevel overlay measurement.

13. The method of claim 9 , wherein the first alignment mark includes a plurality of first alignment marks, and
wherein at least one alignment mark from the plurality of first alignment marks has a different shape than another one of the alignment marks from the plurality of first alignment marks.

14. The method of claim 9 , further comprising:
receiving a layout of the integrated circuit;
diving the layout into a first mask region, a second mask region and a third mask region; and
fabricating the first photomask based on the first mask region, the second photomask based on the second mask region and the third photomask based on the third mask region.

15. The method of claim 9 , wherein the using of the first photomask, the second photomask and the third photomask to form the integrated circuit includes exposing the same photoresist layer using the first, second and third photomasks.

16. A method comprising:
using a first photomask to form a semiconductor device, the first photomask including:
a first die area including a first portion of a first mask feature and a first portion of a second mask feature for forming the semiconductor device;
a first stitching area disposed along a boundary of the first die area, the first stitching region including a second portion of the first mask feature and a first alignment mark for in-chip overlay measurement;
a second stitching area disposed along the boundary of the first die area, the second stitching region including a second portion of the second mask feature and a second alignment mark for in-chip overlay measurement; and
a third stitching area disposed along the boundary of the first die area and positioned between the first stitching area and the second stitching area, the third stitching area being free of any mask feature for forming the semiconductor device.

17. The method of claim 16 , wherein the second portion of the first mask feature has a different size than the first portion of the first mask feature, and
wherein the second portion of the second mask feature has a different size than the first portion of the second mask feature.

18. The method of claim 16 , wherein the first photomask further includes a frame area having a scribe line area and a third alignment for interlevel overlay measurement.

19. The method of claim 16 , wherein the first, second and third alignment marks have different shapes from each other.

20. The method of claim 16 , further comprising using a second photomask to form the semiconductor device, the second photomask including:
a second die area including a third portion of the first mask feature;
a fourth stitching area disposed along a boundary of the second die area, the fourth stitching region including a fourth portion of the first mask feature and a third alignment mark for in-chip overlay measurement, and
wherein the using of the first and second photomasks to form the semiconductor device includes exposing the same photoresist layer using the first and second photomasks.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Peter
• Hsu Chih-Tung
• Wang Kevin
• Hu Chih-Chia
• Chen Roger

Classifications

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G03F1/42

  Alignment or registration features, e.g. alignment marks on the mask substrates · CPC title

• G03F1/38 Primary

  Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof · CPC title

• G03F1/00

  Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof · CPC title

• G03F7/70475 Primary

  Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display · CPC title