Multiple-mask multiple-exposure lithography and masks

Patent metadata

Field	Value
Publication number	US-10620530-B2
Application number	US-201715800140-A
Country	US
Kind code	B2
Filing date	Nov 1, 2017
Priority date	Jul 31, 2017
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

First claim

What is claimed is:

1. A photomask comprising:
a die area; and
a stitching region disposed adjacent to the die area and along a boundary of the photomask, wherein the stitching region includes:
a mask feature for forming an integrated circuit feature; and
an alignment mark for in-chip overlay measurement.

2. The photomask of claim 1 , wherein:
the stitching region further includes a first plurality of alignment marks that includes the alignment mark; and
the first plurality of alignment marks are arranged in parallel with the boundary.

3. The photomask of claim 2 , wherein the stitching region further includes a second plurality of alignment marks arranged in parallel with the boundary and disposed between the first plurality of alignment marks and the boundary.

4. The photomask of claim 3 , wherein:
the first plurality of alignment marks includes an outer box of a first box-in-box pattern; and
the second plurality of alignment marks includes an inner box of a second box-in-box pattern.

5. The photomask of claim 1 , wherein:
the boundary is a first boundary of the photomask;
the alignment mark is a first alignment mark and is for in-chip overlay measurement with respect to a first adjacent photomask;
the stitching region is a first stitching region and is to overlap with an exposure area of the first adjacent photomask;
the photomask further comprises a second stitching region disposed adjacent to the die area and along a second boundary of the photomask; and
the second stitching region is to overlap with an exposure area of a second adjacent photomask and includes a second alignment mark for in-chip overlay measurement with respect to the second adjacent photomask.

6. The photomask of claim 5 , wherein the first boundary is perpendicular to the second boundary.

7. The photomask of claim 1 , wherein:
the alignment mark is a first alignment mark and is for in-chip overlay measurement with respect to a first adjacent photomask;
the photomask further comprises a frame area around the die area; and
the frame area includes a second alignment mark for in-chip overlay measurement with respect to the first adjacent photomask.

8. The photomask of claim 1 , wherein the mask feature extends to the boundary.

9. The photomask of claim 1 , wherein the mask feature extends into the die area.

10. A mask comprising:
a plurality of mask features extending to a boundary of the mask; and
a first plurality of alignment regions containing a first plurality of in-chip alignment features aligned in parallel with the boundary, wherein:
the first plurality of alignment regions overlap with an exposure area of an adjacent mask; and
the first plurality of in-chip alignment features are for overlay measurement with respect to the adjacent mask.

11. The mask of claim 10 further comprising:
a second plurality of alignment regions containing a second plurality of in-chip alignment features aligned in parallel with the boundary disposed between the first plurality of alignment regions and the boundary.

12. The mask of claim 11 further comprising:
a test line extending in parallel with the boundary and disposed between the first plurality of alignment regions and the second plurality of alignment regions, wherein the test line is for overlay measurement with respect to the adjacent mask.

13. The mask of claim 10 , wherein:
the boundary is a first boundary;
the adjacent mask is a first adjacent mask;
the mask further comprises a second plurality of alignment regions containing a second plurality of in-chip alignment features aligned in parallel with a second boundary;
the second plurality of alignment regions overlap with an exposure area of a second adjacent mask; and
the second plurality of in-chip alignment features are for overlay measurement with respect to the second adjacent mask.

14. The mask of claim 10 , wherein the first plurality of in-chip alignment features include a feature from a group consisting of: an inner box alignment feature, an outer box alignment feature, an inner cross alignment feature, an outer cross alignment feature, and a test line.

15. The mask of claim 10 further comprising a frame area, wherein the frame area includes an alignment feature for overlay measurement with respect to the adjacent mask.

16. A mask comprising:
a die area including a mask feature, the mask feature designating a functional feature of an integrated circuit; and
a stitching region disposed along an outer boundary of the mask, wherein the stitching region includes:
the mask feature extending to the outer boundary of the mask; and
an alignment mark for in-chip overlay measurement.

17. The mask of claim 16 , wherein the alignment mark includes a feature selected from the group consisting of an inner box alignment feature, an outer box alignment feature, an inner cross alignment feature, an outer cross alignment feature, and a test line.

18. The mask of claim 16 , wherein the stitching region is operable to overlap with an exposure area of another mask.

19. The mask of claim 16
wherein the mask feature has a first width outside the stitching region and a second width inside the stitching region, and wherein the first width is larger than the second width.

20. The mask of claim 16 , wherein the mask further includes a frame area around the die area, and
wherein the frame area includes a second alignment mark for in-chip overlay measurement with respect to another mask.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Peter
• Hsu Chih-Tung
• Wang Kevin
• Hu Chih-Chia
• Chen Roger

Classifications

• G03F1/42 Primary

  Alignment or registration features, e.g. alignment marks on the mask substrates · CPC title

• G03F1/70 Primary

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G03F1/38 Primary

  Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof · CPC title

• G03F1/144

  Physics · mapped topic

• G03F7/2022

  Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure · CPC title