Device and method of very high density routing used with embedded multi-die interconnect bridge

Patent metadata

Field	Value
Publication number	US-12040276-B2
Application number	US-202217888177-A
Country	US
Kind code	B2
Filing date	Aug 15, 2022
Priority date	Sep 30, 2016
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of alternating patterned first conducting and first insulating layers;
an interconnect bridge above the plurality of alternating patterned conducting and insulating layers;
a plurality of conductive pillars adjacent to sides of the interconnect bridge, the plurality of conducive pillars having a same height as the interconnect bridge;
a second insulating layer laterally between the plurality of conductive pillars and the interconnect bridge;
a third insulating layer above and on the second insulating layer, above and in direct contact with an uppermost surface of the plurality of conductive pillars, and above and on the interconnect bridge, the third insulating layer having a bottommost surface;
a plurality of vias in the third insulating layer, the plurality of vias coupled to the conductive pillars and to the interconnect bridge, wherein the plurality of vias have a bottommost surface at a same level as the bottommost surface of the third insulating layer;
a plurality of traces above and on the third insulating layer;
a first die above the plurality of traces, the first die coupled to the interconnect bridge and to the plurality of conductive pillars;
a second die above the plurality of traces, the second die coupled to the interconnect bridge and to the plurality of conductive pillars; and
a fourth insulating layer over the third insulating layer, the fourth insulating layer intervening between the third insulating layer and the first die, and the fourth insulating layer intervening between the third insulating layer and the second die.

2. The semiconductor device of claim 1 , wherein the interconnect bridge couples the first die to the second die.

3. The semiconductor device of claim 1 , further comprising:
a solder resist layer on the plurality of traces.

4. The semiconductor device of claim 3 , further comprising:
a second plurality of vias in the solder resist layer.

5. The semiconductor device of claim 3 , wherein the solder resist has a thickness in the range of 10-30 microns.

6. The semiconductor device of claim 1 , further comprising:
a monolithic core between the interconnect bridge and the plurality of alternating patterning first conducting and first insulating layers.

7. The semiconductor device of claim 1 , wherein the first die comprises contacts having at most a 40 micron center-to-center pitch.

8. The semiconductor device of claim 7 , wherein the second die comprises contacts having at most a 40 micron center-to-center pitch.

9. A system, comprising:
a memory; and
a processor coupled to the memory, the processor, comprising:
a plurality of alternating patterned first conducting and first insulating layers;
an interconnect bridge above the plurality of alternating patterned conducting and insulating layers;
a plurality of conductive pillars adjacent to sides of the interconnect bridge, the plurality of conducive pillars having a same height as the interconnect bridge;
a second insulating layer laterally between the plurality of conductive pillars and the interconnect bridge;
a third insulating layer above and on the second insulating layer, above and in direct contact with an uppermost surface of the plurality of conductive pillars, and above and on the interconnect bridge, the third insulating layer having a bottommost surface;
a plurality of vias in the third insulating layer, the plurality of vias coupled to the conductive pillars and to the interconnect bridge, wherein the plurality of vias have a bottommost surface at a same level as the bottommost surface of the third insulating layer;
a plurality of traces above and on the third insulating layer;
a first die above the plurality of traces, the first die coupled to the interconnect bridge and to the plurality of conductive pillars;
a second die above the plurality of traces, the second die coupled to the interconnect bridge and to the plurality of conductive pillars; and
a fourth insulating layer over the third insulating layer, the fourth insulating layer intervening between the third insulating layer and the first die, and the fourth insulating layer intervening between the third insulating layer and the second die.

10. The system of claim 9 , further comprising:
a chipset coupled to the processor.

11. The system of claim 9 , further comprising:
a display device coupled to the processor.

12. The system of claim 9 , further comprising:
a smart TV coupled to the processor.

13. The system of claim 9 , further comprising:
a network coupled to the processor.

14. The system of claim 9 , wherein the interconnect bridge couples the first die to the second die.

15. The system of claim 9 , further comprising:
a solder resist layer on the plurality of traces.

16. The system of claim 15 , further comprising:
a second plurality of vias in the solder resist layer.

17. The system of claim 15 , wherein the solder resist has a thickness in the range of 10-30 microns.

18. The system of claim 9 , further comprising:
a monolithic core between the interconnect bridge and the plurality of alternating patterning first conducting and first insulating layers.

19. The system of claim 9 , wherein the first die comprises contacts having at most a 40 micron center-to-center pitch.

20. The system of claim 19 , wherein the second die comprises contacts having at most a 40 micron center-to-center pitch.

Assignees

• Intel Corp

Inventors

• May Robert Alan
• Jen Wei-Lun Kane
• Rosch Jonathan L
• Salama Islam A
• Darmawikarta Kristof

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/227

  Multiple bumps having different sizes · CPC title