Three-dimensional memory devices and fabricating methods thereof

Patent metadata

Field	Value
Publication number	US-12035523-B2
Application number	US-202117532675-A
Country	US
Kind code	B2
Filing date	Nov 22, 2021
Priority date	Nov 28, 2019
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a structure strengthen plug in an upper portion of the alternating dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a gate line silt in the alternating dielectric stack to expose a sidewall of one enlarged connecting portion of the structure strengthen plug; and forming a gate line slit structure in the gate line slit including an enlarged end portion connected to the one enlarged connecting portion of the structure strengthen plug.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
an alternating conductive/dielectric stack on a substrate;
a structure strengthen plug in an upper portion of the alternating conductive/dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; and
a gate line slit structure in the alternating conductive/dielectric stack, wherein the gate line slit structure extends in a word line direction and includes an enlarged end portion connected to one enlarged connecting portion of the structure strengthen plug.

2. The 3D memory device of claim 1 , further comprising:
a top selective gate cut in the upper portion of the alternating conductive/dielectric stack and extending in the word line direction;
wherein the top selective gate cut and the structure strengthen plug comprise a same material.

3. The 3D memory device of claim 1 , wherein:
the structure strengthen plug has the narrow support body with a smaller width in the bit line direction and two enlarged connecting portions with a larger width in the bit line direction arranged at two ends in the word line direction.

4. The 3D memory device of claim 1 , further comprising:
an array of channel structures in the alternating conductive/dielectric stack and between the gate line slit structure and the top selective gate cut.

5. The 3D memory device of claim 4 , wherein each of the channel structures comprises:
a functional layer on a sidewall of a channel hole;
a dielectric filling structure filling each channel hole; and
a channel layer between the functional layer and the dielectric filling.

6. The 3D memory device of claim 4 , wherein:
the array of channel structures includes an even number of rows of channel structures; and
each row of channel structures is arranged staggered with an adjacent row of channel structures.

7. The 3D memory device of claim 1 , wherein:
the gate line slit structures comprises a lower conductive wall, an upper conductive wall, and a gate line slit glue layer between the lower conductive wall and the upper conductive wall.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xu Wenxiang
• Yang Haohao
• Huang Pan
• Yan Ping
• Huo Zongliang
• Zhou Wenbin
• Xu Wei

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10B43/30

  characterised by the memory core region · CPC title

• H10B41/30

  characterised by the memory core region · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title