Semiconductor device having slit between stacks and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-9601509-B1
Application number	US-201614996556-A
Country	US
Kind code	B1
Filing date	Jan 15, 2016
Priority date	Aug 24, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

The present disclosure may provide a semiconductor device having a three-dimensional memory device with improved performance and reliability. The device may include a pipe gate having a pipe channel film embedded in the pipe gate. The device may include source-side channel and drain-side channel films coupled respectively to both ends of the pipe channel film. The device may include interlayer insulation films and conductive patterns alternately stacked and disposed over the pipe gate, the alternately stacked interlayer insulation films and conductive patterns surrounding the source-side channel film and the drain-side channel film. The device may include a slit disposed between the drain-side channel film and the source-side channel film and dividing the alternately stacked interlayer insulation films and conductive patterns into a source-side stack and a drain-side stack, the slit having a round shape at a bottom of the slit adjacent to the pipe gate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a pipe gate having a pipe channel film embedded in the pipe gate;
source-side channel and drain-side channel films coupled respectively to both ends of the pipe channel film;
interlayer insulation films and conductive patterns alternately stacked and disposed over the pipe gate, the alternately stacked interlayer insulation films and conductive patterns surrounding the source-side channel film and the drain-side channel film; and
a slit disposed between the drain-side channel film and the source-side channel film and dividing the alternately stacked interlayer insulation films and conductive patterns into a source-side stack and a drain-side stack, the slit having a round portion at a bottom of the slit,
wherein the round portion of the slit is adjacent to the pipe gate to reduce an electric field concentration on a pipe transistor coupled to the pipe gate.

2. The device of claim 1 , wherein the conductive patterns include a lower conductive pattern adjacent to the pipe gate, the lower conductive pattern being made of materials films that are different from one another and vertically arranged.

3. The device of claim 1 , wherein the conductive patterns include a lower conductive pattern adjacent to the pipe gate, the lower conductive pattern including a stack of first and second conductive films.

4. The device of claim 3 , wherein the lower conductive pattern further includes an anti-reaction film between the first conductive film and the second conductive film.

5. The device of claim 4 , wherein the anti-reaction film includes a metal nitride film.

6. The device of claim 3 , wherein the first conductive film includes a metal film.

7. The device of claim 3 , wherein the second conductive film is made of the same material as the pipe gate.

8. The device of claim 3 , wherein the conductive patterns include main conductive patterns disposed above the lower conductive pattern, and the second conductive film is made of a different material from the main conductive patterns.

9. The device of claim 3 , wherein the second conductive film includes polysilicon.

10. The device of claim 1 , wherein the bottom of the slit is spaced apart from the pipe gate.

Assignees

• Sk Hynix Inc

Inventors

• Shin Wan Cheul

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic

• H01L27/11551

  Electricity · mapped topic

• H01L21/8221

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic