Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9564451-B1
Application number	US-201615094016-A
Country	US
Kind code	B1
Filing date	Apr 8, 2016
Priority date	Nov 6, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A semiconductor device may include a substrate, conductive patterns stacked to be spaced apart from each other on the substrate, contact plugs coming in contact with the respective conductive patterns, and first and second slit insulating layers of a first group penetrating the conductive patterns. The substrate may include a cell area and a contact area extending along a first direction from the cell area. The conductive patterns may be form a step structure. The first slit insulating layers of the first group may be opposite to each other in a second direction with any one of the contact plugs, interposed therebetween. The second slit insulating layers of the first group, which extend along the first direction in the contact area, may be opposite to each other in the second direction with the first slit insulating layers of the first group and the contact plugs, interposed therebetween.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a cell area and a contact area extending along a first direction from the cell area;
conductive patterns stacked to be spaced apart from each other on the substrate and forming a step structure in the contact area;
contact plugs coming in contact with the respective conductive patterns and extending along a direction along which the conductive patterns are stacked;
first slit insulating layers of a first group disposed opposite to each other in a second direction intersecting the first direction with any one of the contact plugs, interposed therebetween, the first slit insulating layers of a first group penetrating the conductive patterns; and
second slit insulating layers of a first group, which extend along the first direction in the contact area to penetrate the conductive patterns, and are disposed opposite to each other in the second direction with the first slit insulating layers of the first group and the contact plugs, interposed therebetween.

2. The semiconductor device of claim 1 , further comprising first slit insulating layers of a second group, which are disposed opposite to each other in the first direction with any one of the contact plugs, interposed therebetween, and disposed between the second slit insulating layers of the first group to penetrate the conductive patterns.

3. The semiconductor device of claim 2 , wherein the first slit insulating layers of the second group and the contact plugs are alternately disposed along the first direction.

4. The semiconductor device of claim 2 , further comprising first slit insulating layers of a third group, which extend along the first direction, are disposed opposite to each other in the second direction, and isolate the conductive patterns to form stacked structures of memory blocks.

5. The semiconductor device of claim 4 , wherein the first slit insulating layers of the first group, the second slit insulating layers of the first group, and the first slit insulating layers of the second group are spaced apart from each other between the first slit insulating layers of the third group.

6. The semiconductor device of claim 1 , further comprising:
channel layers penetrating the conductive patterns on the cell area; and
second slit insulating layers of a second group, which penetrate the conductive patterns between the channel layers, and extend along the first direction.

7. The semiconductor device of claim 1 , wherein the first slit insulating layers of the first group are formed to have a different depth from the second slit insulating layers of the first group.

8. The semiconductor device of claim 1 , further comprising blocking insulating layers respectively disposed between the conductive patterns and the first slit insulating layers, the blocking insulating layers extending along the shape of surfaces of the conductive patterns.

9. The semiconductor device of claim 8 , wherein the blocking insulating layers in a shape that has openings at sidewalls of the conductive patterns, which face the second slit insulating layers of the first group.

10. The semiconductor device of claim 1 , wherein the second slit insulating layers of the first group come in contact with the sidewalls of the conductive patterns.

11. A method of manufacturing a semiconductor device, the method comprising:
alternately stacking first material layers and second material layers on a substrate including a cell area and a contact area extending along a first direction from the cell area;
forming a step structure on the contact area by etching at least a portion of the first material layers and the second material layers;
forming a planarization insulating layer covering the step structure;
forming, in the contact area, first slit insulating layers of a first group, which penetrate the planarization insulating layer, the first material layers, and the second material layers, and are disposed opposite to each other in a second direction intersecting the first direction; and
forming second slits of a first group, which extend along the first direction to penetrate the first material layers and the second material layers, and are disposed opposite to each other in the second direction with the first slit insulating layers of the first group adjacent to each other in the second direction, which are interposed therebetween.

12. The method of claim 11 , further comprising simultaneously forming, together with the first slit insulating layers of the first group, first slit insulating layers of a second group, which are disposed opposite to each other in the first direction with a pad area defined between the first slit insulating layers of the first group adjacent to each other in the second direction, which are interposed therebetween, and are spaced apart from the first slit insulating layers of the first group.

13. The method of claim 11 , further comprising simultaneously forming, together with the first slit insulating layers of the first group, first slit insulating layers of a third group, which isolate the first material layers and the second material layers in units of memory blocks.

14. The method of claim 11 , further comprising:
before forming the second slits of the first group, forming channel layers penetrating the first material layers and the second material layers in the cell area; and
simultaneously forming, together with the second slits of the first group, second slits of the second group, which penetrate the first material layers and the second material layers between the channel layers, and extend along the first direction.

15. The method of claim 14 , further comprising:
forming openings by selectively removing at least a portion of the second material layers exposed through the second slits of the first and second groups;
forming a blocking insulating layer along surfaces of the openings; and
forming third material layers in the respective openings on the blocking insulating layer.

16. The method of claim 15 , wherein the openings are formed to expose sidewalls of the first slit insulating layers of the first group.

17. The method of claim 15 , further comprising forming a contact plug disposed between the first slit insulating layers of the first group, which are adjacent to each other in the second direction, the contact plug penetrating at least one of the planarization insulating layer and the first material layers to come in contact with any one of the third material layers.

18. The method of claim 17 , wherein the contact plug penetrates the blocking insulating layer.

19. The method of claim 11 , wherein the second slits of the first group are formed to have a different depth from the first slit insulating layers of the first group.

Assignees

• Sk Hynix Inc

Inventors

• Shin Hack Seob
• Nam Sang Hyuk
• Park Byung Soo
• Jung Jong Ho

Classifications

• H10W70/095

  of vias therein · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title