Semiconductor devices having unit cell transistors with smoothed turn-on behavior and improved linearity

Patent metadata

Field	Value
Publication number	US-12034072-B2
Application number	US-202117190559-A
Country	US
Kind code	B2
Filing date	Mar 3, 2021
Priority date	Jun 21, 2017
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of unit cell transistors on a semiconductor structure, the semiconductor structure including a gallium nitride based barrier layer, the unit cell transistors electrically connected in parallel, and each of the unit cell transistors including a respective gate finger; and
a voltage divider circuit that includes a first output that is coupled to the respective gate fingers of a first subset of the unit cell transistors and a second output that is coupled to the respective gate fingers of a second subset of the unit cell transistors,
wherein the first and second outputs are configured to apply first and second voltages to the respective gate fingers of the first and second subsets of the unit cell transistors, respectively,
wherein the first and second voltages differ by at least 0.1 volts.

2. The semiconductor device of claim 1 , wherein the unit cell transistors of the first and second subsets of unit cell transistors have identical designs.

3. The semiconductor device of claim 1 , wherein the first and second voltages differ by at least 0.25 volts.

4. The semiconductor device of claim 1 , wherein the voltage divider circuit includes a third output that is coupled to the respective gate fingers of a third subset of the unit cell transistors, wherein the third output is configured to apply a third voltage to the respective gate fingers of the third subset of the unit cell transistors, the third voltage differing from both the first and second voltages by at least 0.1 volts.

5. The semiconductor device of claim 1 , wherein the first and second voltages differ by between 0.1-1.25 volts.

6. The semiconductor device of claim 1 , wherein the plurality of unit cell transistors and at least a portion of the voltage divider circuit are implemented on a common wafer.

7. The semiconductor device of claim 1 , wherein the voltage divider circuit includes a first resistor that is disposed between a voltage source and the gate fingers of the first subset of the unit cell transistors and a second resistor that is disposed between the voltage source and the gate fingers of the second subset of the unit cell transistors.

8. The semiconductor device of claim 7 , wherein a first inductor is provided in series with the first resistor and a second inductor is provided in series with the second resistor.

9. The semiconductor device of claim 8 , wherein the first and second resistors and the plurality of unit cell transistors are implemented on a common wafer.

10. The semiconductor device of claim 9 , wherein the first and second inductors are also implemented on the common wafer.

11. A semiconductor device, comprising:
a wafer having a gallium nitride based layer;
a plurality of unit cell transistors on/in the wafer, the unit cell transistors electrically connected in parallel and each of the unit cell transistors including a respective gate finger; and
a voltage divider circuit that is at least partially on the wafer, the voltage divider circuit including a first output that is coupled to gate fingers of a first subset of the unit cell transistors, a second output that is coupled to gate fingers of a second subset of the unit cell transistors, and a first resistor that is coupled between the first output and the second output.

12. The semiconductor device of claim 11 , wherein the voltage divider circuit further includes a first inductor that is electrically coupled in series with the first resistor.

13. The semiconductor device of claim 11 , wherein the voltage divider circuit further includes a direct current voltage source and a first inductor that is provided between the direct current voltage source and the first output, where the first inductor is implemented off of the wafer.

14. The semiconductor device of claim 12 , wherein the first inductor comprises a meandered conductive line on the wafer.

15. The semiconductor device of claim 11 , wherein the voltage divider circuit further includes a third output that is coupled to gate fingers of a third subset of the unit cell transistors and a second resistor that is coupled between the second output and the third output.

16. The semiconductor device of claim 15 , wherein the voltage divider circuit further includes a second inductor that is electrically coupled in series with the second resistor.

17. The semiconductor device of claim 11 , wherein the first resistor comprises an oxidized portion of a conductive line.

18. The semiconductor device of claim 11 , wherein the first and second outputs are configured to apply first and second voltages to the gate fingers of the first and second subsets of the unit cell transistors, respectively, wherein the first and second voltages differ by at least 0.5 volts.

19. The semiconductor device of claim 15 , wherein the voltage divider circuit further includes a first inductor that is electrically coupled in series with the first resistor and a second inductor that is electrically coupled in series with the second resistor.

20. The semiconductor device of claim 11 , wherein the unit cell transistors of the first and second subsets of unit cell transistors have identical designs.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Liu Yueying
• Sriram Saptharishi
• Sheppard Scott
• Gao Jennifer

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D84/82 Primary

  of only field-effect components · CPC title

• H10D64/411

  for FETs · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title