Device and method of very high density routing used with embedded multi-die interconnect bridge

Patent metadata

Field	Value
Publication number	US-12014989-B2
Application number	US-202218091048-A
Country	US
Kind code	B2
Filing date	Dec 29, 2022
Priority date	Sep 30, 2016
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

First claim

What is claimed is:

1. A semiconductor device, comprising:
alternating layers of dielectric material and metal;
a bridge die above the alternating layers of dielectric material and metal;
a plurality of conductive pillars adjacent to sides of the bridge die;
a first insulating layer above the alternating layers of dielectric material and metal, the first insulating layer laterally between the plurality of conductive pillars and the bridge die;
a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the plurality of conductive pillars, and over the bridge die, the second insulating layer having a bottommost surface;
a plurality of vias in the second insulating layer, the plurality of vias coupled to the plurality of conductive pillars and to the bridge die, wherein the plurality of vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer;
a first die coupled to the bridge die and to the plurality of conductive pillars;
a second die coupled to the bridge die and to the plurality of conductive pillars; and
a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die, and the third insulating layer intervening between the second insulating layer and the second die.

2. The semiconductor device of claim 1 , wherein one of the plurality of vias is offset from a central vertical access of a corresponding one the plurality of conductive pillars.

3. The semiconductor device of claim 1 , wherein the plurality of vias is electrically connected to the plurality of conductive pillars and to the bridge die.

4. The semiconductor device of claim 1 , wherein a first portion of the plurality of vias coupled to the plurality of conductive pillars has a pitch greater than a pitch of a second portion of the plurality of vias coupled to the bridge die.

5. The semiconductor device of claim 1 , wherein the first die is a CPU die, and the second die is a memory die.

6. The semiconductor device of claim 1 , wherein the first die is a first CPU die, and the second die is a second CPU die.

7. The semiconductor device of claim 1 , wherein the first die is a first memory die, and the second die is a second memory die.

8. The semiconductor device of claim 1 , wherein the first die and the second die are electrically coupled to the bridge die and to the plurality of conductive pillars.

9. A semiconductor device, comprising:
a first metal layer;
a first dielectric material layer above the first metal layer;
a second metal layer above the first dielectric material layer;
a second dielectric material layer above the second metal layer;
a bridge die above the second dielectric material layer;
first and second conductive pillars adjacent to a first side of the bridge die;
third and fourth conductive pillars adjacent to a second side of the bridge die, the second side laterally opposite to the first side;
a first insulating layer above the second dielectric material layer, the first insulating layer laterally between the first and second conductive pillars, laterally between the second conductive pillar and the bridge die, laterally between the bridge die and the third conductive pillar, and laterally between the third and fourth conductive pillars;
a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the first conductive pillar, over and in direct contact with an uppermost surface of the second conductive pillar, over and in direct contact with an uppermost surface of the third conductive pillar, and over and in direct contact with an uppermost surface of the fourth conductive pillar, and over the bridge die, the second insulating layer having a bottommost surface;
vias in the second insulating layer, the vias coupled to the first, second, third and fourth conductive pillars to the bridge die, wherein the vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer;
a first die electrically coupled to the bridge die and to the first and second conductive pillars;
a second die electrically coupled to the bridge die and to the third and fourth conductive pillars; and
a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die, and the third insulating layer intervening between the second insulating layer and the second die.

10. The semiconductor device of claim 9 , wherein one of the vias is coupled to and offset from a central vertical access of the third conductive pillar.

11. The semiconductor device of claim 9 , wherein a first portion of the plurality of vias coupled to the first, second, third and fourth conductive pillars has a pitch greater than a pitch of a second portion of the plurality of vias coupled to the bridge die.

12. The semiconductor device of claim 9 , wherein the first die is a first CPU die, and the second die is a second CPU die.

13. A method of fabricating a semiconductor device, the method comprising:
forming alternating layers of dielectric material and metal;
providing a bridge die above the alternating layers of dielectric material and metal;
forming a plurality of conductive pillars adjacent to sides of the bridge die;
forming a first insulating layer above the alternating layers of dielectric material and metal, the first insulating layer laterally between the plurality of conductive pillars and the bridge die;
forming a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the plurality of conductive pillars, and over the bridge die, the second insulating layer having a bottommost surface;
forming a plurality of vias in the second insulating layer, the plurality of vias coupled to the plurality of conductive pillars and to the bridge die, wherein the plurality of vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer;
coupling a first die to the bridge die and to the plurality of conductive pillars;
coupling a second die to the bridge die and to the plurality of conductive pillars; and
forming a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die, and the third insulating layer intervening between the second insulating layer and the second die.

14. The method of claim 13 , wherein the one of the plurality of vias of offset from a central vertical access of a corresponding one the plurality of conductive pillars.

15. The method of claim 13 , wherein the plurality of vias is electrically connected to the plurality of conductive pillars and to the bridge die.

16. The method of claim 13 , wherein a first portion of the plurality of vias coupled to the plurality of conductive pillars has a pitch greater than a pitch of a second portion of the plurality of vias coupled to the bridge die.

17. The method of claim 13 , wherein the first die is a CPU die, and the second die is a memory die.

18. The method of claim 13 , wherein the first die is a first CPU die, and the second die is a second CPU die.

19. The method of claim 13 , wherein the first die is a first memory die, and the second die is a second memory die.

20. The method of claim 13 , wherein the first die and the second die are electrically coupled to

Assignees

• Intel Corp

Inventors

• May Robert Alan
• Jen Wei-Lun Kane
• Rosch Jonathan L
• Salama Islam A
• Darmawikarta Kristof

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/227

  Multiple bumps having different sizes · CPC title