Memory calibration and margin check

Patent metadata

Field	Value
Publication number	US-12014060-B2
Application number	US-202217929212-A
Country	US
Kind code	B2
Filing date	Sep 1, 2022
Priority date	Sep 1, 2022
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

First claim

What is claimed is:

1. An apparatus comprising:
a memory; and
a memory controller coupled to the memory, wherein the memory controller includes a calibration circuit configured to:
perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states; and
determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states;

wherein the memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states:
set initial memory parameters for the second performance state based on the set of differences; and
begin operation in the second performance state without performing an initial horizontal calibration.

2. The apparatus of claim 1 , wherein a given performance state of one of the plurality of performance states includes a unique combination of an operating voltage and a clock frequency relative to other ones of the plurality of performance states.

3. The apparatus of claim 1 , wherein the calibration circuit is further configured to, subsequent to operating in the second performance state, perform a margin check calibration, wherein to perform the margin check calibration, the calibration circuit is further configured to:
determine if a calibration result at a first point provides passing results, wherein the first point corresponds to a delay value that is less than a calibrated delay point; and
determine if a calibration result at a second point provides passing results, wherein the second point corresponds to a delay value that is greater than the calibrated delay point.

4. The apparatus of claim 3 , wherein the calibration circuit is configured to skip performing a full horizontal calibration in the second performance state in response to determining that the calibration results at the first point and the second point are passing results.

5. The apparatus of claim 3 , wherein the calibration circuit is further configured to:
perform a full horizontal calibration in the second performance state in response to determining that at least one of the calibration results at the first and second points does not pass; and
update the set of differences based on results of the full horizontal calibration.

6. The apparatus of claim 3 , wherein the calibration circuit is further configured to limit, to a threshold value, a number of times that the margin check calibration is performed subsequent to entering the second performance state, and in response to determining that the number of times the margin check calibration has been performed exceeds the threshold, perform a full horizontal calibration instead of the margin check calibration.

7. The apparatus of claim 1 , wherein in performing a horizontal calibration, the calibration circuit is configured to perform writes of data to and reads of data from memory at a particular reference voltage and at differing values of delay applied to a data strobe signal.

8. The apparatus of claim 1 , wherein the memory comprises a multi-rank memory system having a first set of memory circuits and a second set of memory circuits sharing a common set of signal paths between the memory controller and the memory.

9. The apparatus of claim 1 , wherein the calibration circuit is further configured to, subsequent to the initialization process, perform one or more periodic horizontal calibrations during operations in the first one of the plurality of performance states and prior to changing to the second one of the plurality of performance states, and further configured to set initial memory parameters for the second one of the plurality of performance states based on the a most recent horizontal calibration performed in the first one of the plurality of performance states prior transitioning to the second performance state.

10. The apparatus of claim 1 , wherein the initialization process comprises a system startup.

11. A method, comprising:
performing, by a memory controller during an initialization process, horizontal memory calibrations for ones of a plurality of performance states;
determining, by the memory controller, a set of differences between calibration results for pairs of the plurality of performance states;
storing, by the memory controller, information indicative of the set of differences;
subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states:
setting initial memory parameters for the second one of the plurality of performance states that are based on the set of differences; and
beginning operation in the second one of the plurality of performance states using the initial memory parameters without performing an initial horizontal memory calibration.

12. The method of claim 11 , further comprising performing, using a calibration circuit, a margin check calibration, wherein performing the margin check calibration comprises:
determining if a calibration result at a first point provides passing results, wherein the first point corresponds to a delay value that is less than a calibrated delay point; and
determining if a calibration result at a second point provides passing results, wherein the second point corresponds to a delay value that is greater than the calibrated delay point.

13. The method of claim 12 , further comprising skipping performing a full horizontal calibration in the second one of the plurality of performance states in response to determining that calibration results at the first point and the second point are passing results.

14. The method of claim 13 , further comprising performing a full horizontal calibration if at least one of the calibration results from one of the first and second points does not produce a passing result.

15. The method of claim 11 , wherein a given performance state of one of the plurality of performance states includes a unique combination of an operating voltage and a clock frequency relative to other ones of the plurality of performance states.

16. The method of claim 11 , wherein the initialization process comprises a startup routine.

17. A system comprising:
a memory subsystem having a memory controller coupled to a memory, wherein the memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states, and a storage circuit configured to store information indicative of a set of differences between calibration results for pairs of the plurality of performance states; and
a power management circuit configured to change operation of the memory subsystem from a first one of the plurality of performance states to a second one of the plurality of performance states;
wherein the memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states, set initial parameters for the second performance state based on the set of differences and begin operation in the second performance state without performing an initial horizontal calibration.

18. The system of claim 17 , wherein a given performance state of one of the plurality of performance states includes a unique combination o

Assignees

• Apple Inc

Inventors

• Jeter Robert E
• Zheng Jingkui
• Shah Ritesh J
• Chockalingam Veera
• Korada Naveen Kumar

Classifications

• G11C2207/2254

  Calibration · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0632 Primary

  by initialisation or re-initialisation of storage systems · CPC title

• G06F3/0614

  Improving the reliability of storage systems · CPC title