Apparatus and method for memory calibration averaging

Patent metadata

Field	Value
Publication number	US-9666264-B1
Application number	US-201615187886-A
Country	US
Kind code	B1
Filing date	Jun 21, 2016
Priority date	Jun 21, 2016
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A method and apparatus for memory calibration averaging is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller. The memory controller includes a calibration control circuit that periodically performs calibrations of the memory subsystem. Calibration may be performed for a delay applied to a data strobe used to synchronized transfers of data between the memory controller and the memory, and a reference voltage used to distinguish between a logic 0 and a logic 1 during memory reads. Following the performance of a calibration, the values of the delay and the reference voltage may be set based on an average of a most recent number of calibrations.

First claim

What is claimed is:

1. An apparatus comprising:
a memory; and
a memory controller coupled to the memory and configured to convey a data strobe signal to the memory during transfers of data to and from the memory, wherein the memory controller includes:
a calibration control circuit configured to perform periodic calibrations of a delay applied to the data strobe signal and a reference voltage used to distinguish a logic zero from a logic one in data read from the memory, and further configured to set the delay and the reference voltage to an average value of a most recent N calibration iterations;
wherein the calibration control circuit comprises:
a calibration history circuit configured to store results for each iteration of the most recent N calibration iterations; and
a calibration circuit configured to perform the periodic calibrations, wherein the calibration circuit is configured to, during performance of a calibration, cause multiple reads of data at a plurality of different values of the reference voltage.

2. The apparatus as recited in claim 1 , wherein the calibration history circuit comprises N entries, wherein N is an integer number, and wherein each of the N entries is configured to store calibration results for one of the most recent N calibration iterations.

3. The apparatus as recited in claim 1 , wherein the calibration control circuit further comprises a calibration averaging circuit configured to calculate an average of calibration results for each iteration of the most recent N calibration iterations.

4. The apparatus as recited in claim 1 , wherein the calibration circuit is further configured to, during performance of a calibration, cause multiple writes and reads of data at a plurality of different values of the delay.

5. A method comprising:
performing, by a calibration circuit in a memory subsystem, periodic calibrations of a delay applied to the data strobe signal and a reference voltage used to distinguish a logic zero from a logic one in data read from a memory in a memory subsystem, wherein performing the periodic calibrations comprises the calibration circuit causing multiple reads of data at a plurality of different values of the reference voltage; and
subsequent to performing each calibration, setting the delay and reference voltages to calculated average values based on a history of values that includes current calibrated values of the delay and the reference voltage.

6. The method as recited in claim 5 , further comprising storing, in a history buffer, results for each of a most recent N iterations of the periodic calibrations.

7. The method as recited in claim 6 , further comprising, subsequent to each iteration of the periodic calibrations, calculating an average value of each of the delay and the reference voltage based on the results stored in the history buffer.

8. The method as recited in claim 6 , further comprising, subsequent to each iteration of the periodic calibrations:
storing results for a most recently performed calibration in the history buffer; and
evicting oldest results from the history buffer.

9. The method as recited in claim 5 , wherein performing each calibration further comprises performing a plurality of writes to and a plurality of reads from the memory at different delay values.

10. A system comprising:
a memory subsystem having a memory coupled to a memory controller, wherein the memory controller is configured to write data to the memory and read data from the memory, and wherein the memory controller includes:
a calibration control unit comprising circuitry configured to perform periodic calibrations of a reference voltage and delay applied to a data strobe signal, wherein the data strobe signal is used to synchronize transfers of data between the memory controller and the memory, and wherein the reference voltage is used to distinguish a logic zero from a logic one in data read from the memory;
wherein the calibration control unit is further configured to set the delay and the reference voltage to an average value of a most recent N iterations of the periodic calibrations; and
wherein the calibration control unit includes a calibration circuit configured to perform each of the periodic calibrations, wherein the calibration circuit is configured to, during performance of a calibration, cause multiple reads of data at a plurality of different values of the reference voltage.

11. The system as recited in claim 10 , wherein the calibration circuit is configured to set the delay and reference voltage values subsequent to performing a periodic calibration.

12. The system as recited in claim 11 , wherein the calibration control unit includes a history buffer having N entries each configured to store calibration results for one of the most recent N iterations of the periodic calibrations, wherein subsequent to performing a calibration, the calibration control unit circuit is configured to:
evict oldest results from the history buffer; and
store results for a most recently performed calibration in the history buffer.

13. The system as recited in claim 12 , further comprising an averaging circuit configured to calculate average values of the delay and the reference voltage based on the calibration results stored in the history buffer, and further configured to convey the calculated average values to the calibration circuit.

14. The system as recited in claim 13 , wherein the calibration circuit is configured to set values for the delay and the reference voltage responsive to receiving updated average value from the averaging circuit.

15. The system as recited in claim 10 , wherein the calibration circuit is configured to, during performance of a calibration, cause multiple writes and reads of data at a plurality of different values of the delay.

Assignees

• Apple Inc

Inventors

• Jeter Robert E
• Hsiung Kai Lun
• Notani Rakesh L
• Yuan Xingchao C

Classifications

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F13/4234 Primary

  being a memory bus · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C7/1093

  Input synchronization · CPC title