Memory Calibration and Margin Check
US-2026023491-A1 · Jan 22, 2026 · US
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Chockalingam Veera patents
Chockalingam Veera is listed as an inventor on 5 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chockalingam Veera |
| Total patents | 5 |
| First publication | Mar 7, 2024 |
| Latest publication | Jan 22, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory calibration and margin check
US-12399634-B2 · Aug 26, 2025 · US
Memory Calibration and Margin Check
US-2024295976-A1 · Sep 5, 2024 · US
Memory calibration and margin check
US-12014060-B2 · Jun 18, 2024 · US
Memory Calibration and Margin Check
US-2024078029-A1 · Mar 7, 2024 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Apple Inc | 5 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C2207/2254 | 5 |
| G06F3/0673 | 5 |
| G06F3/0658 | 5 |
| G06F3/0632 | 5 |
| G06F3/0614 | 5 |