Self aligned top contact for vertical transistor

Patent metadata

Field	Value
Publication number	US-12009422-B2
Application number	US-202117453874-A
Country	US
Kind code	B2
Filing date	Nov 8, 2021
Priority date	Nov 8, 2021
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A semiconductor structure including a bottom source drain region arranged on a substrate; a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region; a metal gate disposed around the semiconductor channel region; a top source drain region above the semiconductor channel region; and a top contact partially embedded into the top source drain region.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed around the semiconductor channel region;
a top source drain region above the semiconductor channel region; and
a top contact partially embedded into the top source drain region
a dielectric spacer separating the metal gate from the top source drain region, wherein a width of the dielectric spacer is substantially equal to a width of the top source drain region.

2. The semiconductor structure according to claim 1 ,
wherein a width of the top source drain region is substantially equal to a combined width of the metal gate and the gate dielectric.

3. The semiconductor structure according to claim 1 , further comprising:
a bottom spacer separating the bottom source drain region from the metal gate.

4. The semiconductor structure according to claim 1 , wherein a width of a lower portion of the top contact is smaller than a width of an upper portion of the top contact.

5. The semiconductor structure according to claim 1 , wherein a lower portion of the top contact is surrounded by the top source drain region and directly contacts a top surface of the semiconductor channel region.

6. The semiconductor structure according to claim 1 , wherein a bottom surface of an upper portion of the top contact covers a top surface of the top source drain region.

7. The semiconductor structure according to claim 1 , wherein a bottom surface of the top source drain region is below a top surface of the semiconductor channel region.

8. A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed around the semiconductor channel region;
a top source drain region above the semiconductor channel region;
a top contact partially embedded into the top source drain region, wherein sidewalls of the top contact are flush or substantially flush with sidewalls of the channel region; and
a gate liner separating the metal gate and the top source drain from an interlevel dielectric layer, wherein an uppermost surface of the gate liner is substantially flush with an uppermost surface of the top source drain region.

9. The semiconductor structure according to claim 8 , further comprising:
a dielectric spacer separating the metal gate from the top source drain region.

10. The semiconductor structure according to claim 8 , further comprising:
a bottom spacer separating the bottom source drain region from the metal gate.

11. The semiconductor structure according to claim 8 , wherein a width of a lower portion of the top contact is smaller than a width of an upper portion of the top contact.

12. The semiconductor structure according to claim 8 , wherein a lower portion of the top contact is surrounded by the top source drain region and directly contacts a top surface of the semiconductor channel region.

13. The semiconductor structure according to claim 8 , wherein a bottom surface of an upper portion of the top contact covers a top surface of the top source drain region.

14. The semiconductor structure according to claim 8 , wherein a bottom surface of the top source drain region is below a top surface of the semiconductor channel region.

15. A method comprising:
forming a bottom source drain region arranged on a substrate;
forming a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
forming a metal gate disposed around the semiconductor channel region;
forming a dielectric spacer on the metal gate;
forming a top source drain region above the semiconductor channel region, wherein the dielectric spacer separates the metal gate from the top source drain region; and
forming a top contact partially embedded into the top source drain region.

16. The semiconductor structure according to claim 1 ,
wherein a width of the top source drain region is substantially equal to a width of the metal gate plus a lateral width of the gate dielectric.

17. The method according to claim 15 , further comprising:
forming a bottom spacer separating the bottom source drain region from the metal gate.

18. The method according to claim 15 , wherein a width of a lower portion of the top contact is smaller than a width of an upper portion of the top contact.

19. The method according to claim 15 , wherein a lower portion of the top contact is surrounded by the top source drain region and directly contacts a top surface of the semiconductor channel region.

20. The method according to claim 15 , wherein a bottom surface of an upper portion of the top contact covers a top surface of the top source drain region.

Assignees

• IBM

Inventors

• Lee Choonghyun
• Waskiewicz Christopher J
• Park Chanro
• Reznicek Alexander

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title