Metal layer routing level for vertical FET SRAM and logic cell scaling

Patent metadata

Field	Value
Publication number	US-10056377-B2
Application number	US-201715786164-A
Country	US
Kind code	B2
Filing date	Oct 17, 2017
Priority date	Nov 23, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

First claim

What is claimed is:

1. A method comprising:
forming a source/drain (S/D) layer over a substrate;
forming a blanket dielectric layer over the S/D layer;
forming a metal routing layer over the blanket dielectric layer;
patterning the metal routing layer;
forming a replacement metal gate (RMG) stack over the S/D layer and the metal routing layer;
forming a replacement fin trench through the RMG stack down to the S/D layer;
forming a replacement fin stack in the replacement fin trench;
forming a silicon nitride (SiN) cap over the replacement fin wider than the replacement fin;
removing a portion of the RMG stack on each side of the SiN cap; and
forming a gate all around (GAA) on a remaining portion of the RMG stack and around the replacement fin.

2. The method according to claim 1 , comprising forming the S/D layer to a thickness of 5 nanometer (nm) to 50 nm.

3. The method according to claim 1 , further comprising etching the blanket dielectric layer down to the S/D layer in designed contact areas prior to forming the metal routing layer.

4. The method according to claim 1 , comprising patterning the metal routing layer to a width of 3 nm to 50 nm.

5. The method according to claim 1 , comprising forming the RMG stack by:
forming a first silicon boron carbon nitride (SiBCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon carbide (SiC) layer over the S/D layer and the metal routing layer;
forming a first oxide layer over the first SiBCN, SiOC, SiOCN, or SiC layer;
forming a second SiBCN, SiOC, SiOCN, or SiC layer over the first oxide layer; and
forming a second oxide layer over the second SiBCN, SiOC, SiOCN, or SiC layer.

6. The method according to claim 5 , comprising removing the portion of the RMG stack by:
etching the RMG stack down to the first SiBCN, SiOC, SiOCN, or SiC layer on each side of the SiN cap and a portion of the second SiBCN, SiOC, SiOCN, or SiC layer remaining under the SiN cap.

7. The method according to claim 1 , comprising forming the RMG stack by:
forming a first SiN layer over the S/D layer and the metal routing layer;
planarizing the first SiN layer down to the metal routing layer;
forming a second SiN layer over the first SiN layer and the metal routing layer;
forming an oxide layer over the second SiN layer; and
forming a third SiN layer over the oxide layer.

8. The method according to claim 7 , comprising removing the portion of the RMG stack by:
etching the RMG stack down to the second SiN layer on each side of the SiN cap, a portion of the third SiN layer remaining under the SiN cap.

9. The method according to claim 1 , comprising forming the replacement fin stack by:
forming a second S/D layer on the S/D layer in the replacement fin trench;
forming an active fin layer on the second S/D layer; and
forming a third S/D layer on the active fin layer.

10. The method according to claim 1 , comprising forming the replacement fin stack by:
forming an active fin layer on the S/D layer in the replacement fin trench; and
forming a second S/D layer on the active fin layer.

11. The method according to claim 1 , further comprising forming a trench silicide adjacent to the GAA on the metal routing layer to connect the GAA and the metal routing layer.

12. The method according to claim 1 , further comprising forming a dedicated cross-couple (xc) contact through the GAA down to the metal routing layer to connect the GAA and the metal routing layer.

13. A device comprising:
a source/drain (S/D) layer over a substrate;
a metal routing layer over a portion of the S/D layer;
a first fin stack and a second fin stack over respective portions of the S/D layer, each fin stack on an opposite side of the metal routing layer;
a silicon boron carbon nitride (SiBCN) layer or a silicon nitride (SiN) layer over the S/D layer and the metal routing layer;
a gate all around (GAA) over the metal routing layer, a portion of the SiBCN layer or the SiN layer, and around each fin stack;
a second SiBCN layer or a second SiN layer around each fin stack and over a portion of the GAA; and
a silicon nitride (SiN) cap over each fin stack and the SiBCN layer or the SiN layer.

14. The device according to claim 13 , wherein the SiBCN layer is formed over the S/D layer and the metal routing layer, the device comprising:
the second SiBCN around each fin stack.

15. The device according to claim 13 , wherein the SiN layer is formed over the S/D layer and the metal routing layer, the device comprising:
the second SiN layer around each fin stack.

16. The device according to claim 13 , further comprising:
a dielectric layer over non-contact areas of the S/D layer and under portions of the metal routing layer.

17. The device according to claim 13 wherein the metal routing layer comprises a width of 3 nm to 50 nm.

18. The device according to claim 13 , further comprising:
a trench silicide adjacent to the GAA on the metal routing layer to connect the GAA and the metal routing layer.

19. The device according to claim 13 , further comprising:
a dedicated cross-couple (xc) contact through the GAA down to the metal routing layer to connect the GAA and the metal routing layer.

20. A method comprising:
forming a n+/p+ doped source/drain (S/D) layer to a thickness of 5 nanometer (nm) to 50 nm over a substrate;
forming a blanket dielectric layer over the S/D layer;
etching the blanket dielectric layer down to the S/D layer in designed contact areas;
forming a metal routing layer over the blanket dielectric layer and the S/D layer;
patterning the metal routing layer to a width of 3 nm to 50 nm;
forming a replacement metal gate (RMG) stack over the S/D layer and the metal routing layer;
forming a replacement fin trench through the RMG stack down to the S/D layer;
forming a replacement fin stack in the replacement fin trench;
forming a silicon nitride (SiN) cap over the replacement fin wider than the replacement fin;
removing a portion of the RMG stack on each side of the SiN cap;
forming a gate all around (GAA) on a remaining portion of the RMG stack and around the replacement fin; and
forming a trench silicide adjacent to the GAA on the metal routing layer or a dedicated cross-couple (xc) contact through the GAA down to the metal routing layer to connect the GAA and the metal routing layer.

Assignees

• Globalfoundries Inc

Inventors

• Bentley Steven
• Paul Bipul C

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10W72/013

  of die-attach connectors · CPC title