Semiconductor device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-12009325-B2
Application number	US-202117328176-A
Country	US
Kind code	B2
Filing date	May 24, 2021
Priority date	Nov 4, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

First claim

What is claimed is:

1. A semiconductor device, comprising a cell structure stacked on a peripheral circuit structure, wherein:
the cell structure includes:
a plurality of gate electrode layers stacked on a first substrate;
a plurality of channel regions vertically penetrating the gate electrode layers;
a first interlayer dielectric layer on the first substrate and covering the gate electrode layers and the channel regions; and
a plurality of first metal pads exposed at the first interlayer dielectric layer and connected to the gate electrode layers and the channel regions,

the peripheral circuit structure includes:
at least one transistor on a second substrate;
a second interlayer dielectric layer on the second substrate and covering the transistor; and
a plurality of second metal pads exposed at the second interlayer dielectric layer and connected to the transistor,

the plurality of first metal pads include at least one first sub-pad and at least one second sub-pad that are adjacent to each other,
the plurality of second metal pads include at least one third sub-pad and at least one fourth sub-pad that are adjacent to each other,
the at least one first sub-pad and the at least one third sub-pad are coupled to each other, and a width of the at least one first sub-pad is greater than a width of the at least one third sub-pad,
the at least one second sub-pad and the at least one fourth sub-pad are coupled to each other, and a width of the at least one fourth sub-pad is greater than a width of the at least one second sub-pad,
a distance between a lateral surface of the at least one first sub-pad and a lateral surface of the at least one second sub-pad adjacent to the at least one first sub-pad is substantially the same as a distance between a lateral surface of the at least one third sub-pad and a lateral surface of the at least one fourth sub-pad adjacent to the at least one third sub-pad, and
the width of the at least one first sub-pad is substantially the same as the width of the at least one fourth sub-pad, and the width of the at least one second sub-pad is substantially the same as the width of the at least one third sub-pad.

2. The semiconductor device as claimed in claim 1 , wherein, at an interface between the first interlayer dielectric layer and the second interlayer dielectric layer:
an area of the at least one first sub-pad is greater than an area of the at least one third sub-pad such that, when viewed in a plan view, the at least one third sub-pad is in an inside of the at least one first sub-pad, and
an area of the at least one fourth sub-pad is greater than an area of the at least one second sub-pad, and when viewed in a plan, the at least one second sub-pad is in an inside of the at least one fourth sub-pad.

3. The semiconductor device as claimed in claim 1 , wherein:
the at least one first sub-pad includes a plurality of first sub-pads, the at least one second sub-pad includes a plurality of second sub-pads, the at least one third sub-pad includes a plurality of third sub-pads, and the at least one fourth sub-pad includes a plurality of fourth sub-pads, and
the plurality of first sub-pads and the plurality of second sub-pads are alternately arranged in one direction parallel to a top surface of the first substrate.

4. The semiconductor device as claimed in claim 1 , wherein:
the at least one first sub-pad includes a plurality of first sub-pads, the at least one second sub-pad includes a plurality of second sub-pads, the at least one third sub-pad includes a plurality of third sub-pads, and the at least one fourth sub-pad includes a plurality of fourth sub-pads,
the plurality of first sub-pads are on a first region of the first substrate, and
the plurality of second sub-pads are on a second region of the first substrate.

5. The semiconductor device as claimed in claim 1 , wherein,
the plurality of first metal pads further include a fifth sub-pad between the at least one first sub-pad and the at least one second sub-pad,
the plurality of second metal pads further include a sixth sub-pad between the at least one third sub-pad and the at least one fourth sub-pad,
the fifth sub-pad is coupled to the sixth sub-pad, and
a width of the fifth sub-pad is the same as a width of the sixth sub-pad.

6. The semiconductor device as claimed in claim 5 , wherein the fifth sub-pad and the sixth sub-pad are vertically aligned with each other.

7. The semiconductor device as claimed in claim 1 , wherein, at an interface between the first interlayer dielectric layer and the second interlayer dielectric layer:
the at least one first sub-pad and the at least one third sub-pad constitute a single body formed of the same material, and
the at least one second sub-pad and the at least one fourth sub-pad constitute a single body formed of the same material.

8. The semiconductor device as claimed in claim 1 , wherein:
the width of the at least one first sub-pad is greater than the width of the at least one second sub-pad, and
the width of the at least one third sub-pad is less than the width of the at least one fourth sub-pad.

9. The semiconductor device as claimed in claim 1 , wherein the cell structure further includes a memory cell array, the memory cell array including:
a plurality of cell strings including a plurality of memory cells;
a plurality of word lines connected to the plurality of memory cells;
a plurality of bit lines connected to one side of the plurality of cell strings; and
a ground selection line connected to the plurality of cell strings.

10. The semiconductor device as claimed in claim 1 , wherein the distance between the lateral surface of the at least one first sub-pad and the lateral surface of the at least one second sub-pad adjacent to the at least one first sub-pad is about 0.1 μm to about 10 μm.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min
• Kim Jiwon
• Ahn Jaeho
• Lim Joon-Sung
• Sung Sukkang

Classifications

• H10W90/791

  of direct-bonded pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/551

  Materials of bond wires · CPC title