Semiconductor device and imaging device

Patent metadata

Field	Value
Publication number	US-10355039-B2
Application number	US-201615572870-A
Country	US
Kind code	B2
Filing date	Apr 26, 2016
Priority date	May 18, 2015
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer. A width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor chip including a first joining surface including:
a first insulating layer;
a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected; and
a linear first metal layer arranged on an outside of the plurality of first pads; and

a second semiconductor chip including a second joining surface joined to the first joining surface, the second joining surface including:
a second insulating layer;
a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected; and
a linear second metal layer arranged in a position facing the first metal layer,

wherein a width of the first metal layer and the second metal layer is a width based on an average value of a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad, and
wherein the width of the first metal layer and the second metal layer is substantially equal to a width Q satisfying the following relation,
( x×P+y×Q )/ R>z

where
z: a joining strength per unit area between the first semiconductor chip and the second semiconductor chip,
x: a joining strength per unit area between the first insulating layer and the second insulating layer,
y: a joining strength per unit area between the first metal layer and the second metal layer,
P: a length of a joining portion of the first insulating layer and the second insulating layer on a path crossing an end portion of the first semiconductor chip substantially perpendicularly, and
R: a length between the first pad and the end portion of the first semiconductor chip on the path.

2. The semiconductor device according to claim 1 , wherein the path is a path crossing the end portion of the first semiconductor chip substantially perpendicularly, and extending from the end portion of the first semiconductor chip and first reaching the first pad.

3. The semiconductor device according to claim 2 , wherein the path is a path with a longest distance among paths crossing the end portion of the first semiconductor chip substantially perpendicularly, and extending from the end portion of the first semiconductor chip and first reaching the first pad.

4. The semiconductor device according to claim 1 ,
wherein the first joining surface further includes a first dummy pad to which the first inner layer circuit is not electrically connected,
the second joining surface further includes a second dummy pad that is arranged in a position facing the first dummy pad and to which the second interior circuit is not electrically connected, and
the width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area extending from an end portion of the first semiconductor chip and first reaching the first pad or the first dummy pad.

5. The semiconductor device according to claim 1 ,
wherein the first metal layer and the second metal layer are divided into a prescribed number of pieces.

6. The semiconductor device according to claim 1 ,
wherein the first semiconductor chip and the second semiconductor chip are configured in a rectangular shape, and
the width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in the area for each side of each of the first semiconductor chip and the second semiconductor chip.

7. An imaging device comprising:
a first semiconductor chip including:
a first joining surface including:
a first insulating layer;
a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected; and
a linear first metal layer arranged on an outside of the plurality of first pads; and

a first diffusion layer including:
a semiconductor region to which the first inner layer circuit is electrically connected and that converts applied light to an electrical signal; and

a second semiconductor chip joined to the first joining surface, the second semiconductor chip including:
a second joining surface including:
a second insulating layer;
a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected; and
a linear second metal layer arranged in a position facing the first metal layer; and

a second diffusion layer including:
a semiconductor region to which the second inner layer circuit is electrically connected and that processes the electrical signal,

wherein a width of the first metal layer and the second metal layer is a width based on an average value of a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area extending from an end portion of the first semiconductor chip to the first pad, and
wherein the width of the first metal layer and the second metal layer is substantially equal to a width Q satisfying the following relation,
( x×P+y×Q ) R>z

where
z: a joining strength per unit area between the first semiconductor chip and the second semiconductor chip,
x: a joining strength per unit area between the first insulating layer and the second insulating layer,
y: a joining strength per unit area between the first metal layer and the second metal layer,
P: a length of a joining portion of the first insulating layer and the second insulating layer on a path crossing an end portion of the first semiconductor chip substantially perpendicularly, and
R: a length between the first pad and the end portion of the first semiconductor chip on the path.

Assignees

• Sony Corp

Inventors

• Kotoo Kengo
• Koike Kaoru

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/701

  characterised by the pads after the direct bonding · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/163

  using active alignment, e.g. detecting marks and correcting position · CPC title