Switching circuits having ferrite beads

Patent metadata

Field	Value
Publication number	US-2016006428-A1
Application number	US-201414323777-A
Country	US
Kind code	A1
Filing date	Jul 3, 2014
Priority date	Jul 3, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.

First claim

What is claimed is:

1 . A circuit comprising:
an electronic component package comprising at least a first lead; a III-N device in the electronic component package, the III-N device comprising a drain, a gate, and a source, the source coupled to the first lead; a gate driver comprising a first terminal and a second terminal, the first terminal being coupled to the first lead; and a ferrite bead coupled between the gate of the III-N transistor and the second terminal of the gate driver.

2 . The circuit of claim 1 , wherein the second terminal of the gate driver, the ferrite bead, the III-N device, the first lead, and the first terminal form a gate loop; and wherein the first lead has a parasitic inductance and the ferrite bead is configured to reduce oscillations and electromagnetic interference in the gate loop due to the parasitic inductance.

3 . The circuit of claim 1 , wherein the III-N device and the electronic component package form a low side switch, and the first lead is coupled to a ground node, the circuit further comprising a high side switch coupled between the drain of the III-N device and a high voltage node, the high side switch comprising a high side gate coupled to a third terminal of the gate driver.

4 . The circuit of claim 3 , wherein the gate driver is configured to apply a low side control signal to the second terminal relative to the first terminal, and to apply a high side control signal to the third terminal relative to a fourth terminal of the gate driver, the fourth terminal being coupled to a high side source of the high side switch.

5 . The circuit of claim 3 , comprising:
a processor coupled to the gate driver and at least one other gate driver; and memory storing executable instructions that, when executed by the processor, cause the processor to control the gate driver and the other gate driver to operate the circuit as a half bridge.

6 . The circuit of claim 3 , wherein the voltage at the high voltage node relative to the ground node is about 400V or higher.

7 . The circuit of claim 6 , wherein the gate driver is configured to apply a control signal to the second terminal relative to the first terminal, the control signal having a frequency between 30 kHz and 10 MHz.

8 . The circuit of claim 3 , further comprising a second ferrite bead coupled between the high side gate and the third terminal of the gate driver.

9 . The circuit of claim 1 , wherein the gate driver is configured to apply a control signal to the second terminal relative to the first terminal, the control signal having a frequency between 30 kHz and 10 MHz.

10 . The circuit of claim 1 , wherein the III-N device is an enhancement mode transistor.

11 . The circuit of claim 1 , wherein the III-N device is a hybrid device comprising a depletion mode III-N transistor and an enhancement mode silicon transistor.

12 . The circuit of claim 1 , wherein the ferrite bead forms a passive low pass filter configured to block electromagnetic interference having frequencies above 100 MHz.

13 . The circuit of claim 1 , wherein the electronic component package further comprises a second lead, the second lead is coupled to the source and to a ground node, and the first lead is electrically connected to the first terminal of the gate driver.

14 . A circuit comprising:
a gate driver comprising first and second high side output terminals and first and second low side output terminals; a high side III-N device comprising:
a high side gate coupled to the first high side output terminal of the gate driver;
a high side drain coupled to a high voltage node; and
a high side source coupled to a load node;
a low side III-N device comprising:
a low side gate coupled to the first low side output terminal of the gate driver;
a low side drain coupled to the load node; and
a low side source coupled to a ground node; and
a ferrite bead coupled between the high side gate and the first high side output terminal of the gate driver.

15 . The circuit of claim 14 , comprising:
a processor coupled to the gate driver; and memory storing executable instructions that, when executed by the processor, cause the processor to control the gate driver to operate the circuit as a half bridge.

16 . The circuit of claim 14 , wherein during operation of the circuit, the voltage at the high voltage node relative to the ground node is at least 400V.

17 . The circuit of claim 14 , wherein the gate driver is configured to apply control signals to the first high side output terminal relative to the second high side output terminal and to the first low side output terminal relative to the second output terminal, the control signals having a frequency between 30 kHz and 10 MHz.

18 . The circuit of claim 14 , wherein the high side III-N device comprises a III-N enhancement mode transistor.

19 . The circuit of claim 14 , wherein the high side III-N device is a hybrid device comprising a depletion mode III-N transistor and an enhancement mode silicon transistor.

20 . The circuit of claim 14 , wherein the ferrite bead forms a passive low pass filter configured to block electromagnetic interference having frequencies above 100 MHz.

21 . An electronic component comprising:
an electronic package including at least a first lead; a III-N switching device comprising a gate, the III-N switching device encased in the electronic package; and a ferrite bead encased in the electronic package, wherein the ferrite bead is coupled between the gate and the first lead.

22 . The electronic component of claim 21 , wherein the III-N switching device is a hybrid device comprising a depletion mode III-N transistor and an enhancement mode transistor, and the gate is a first gate of the enhancement mode transistor.

23 . The electronic component of claim 22 , the electronic package further comprising a conductive structural base, wherein the depletion mode III-N transistor is a lateral III-N transistor comprising a second gate, and wherein the second gate of the III-N transistor is electrically connected to the conductive structural base of the electronic package.

24 . The electronic component of claim 21 , the electronic package further comprising a conductive structural base, wherein the III-N switching device and the ferrite bead are both mounted on the conductive structural base.

25 . The electronic component of claim 21 , comprising a first wire bond between the ferrite bead and the gate and a second wire bond between the ferrite bead and the first lead.

26 . The electronic component of claim 21 , wherein the III-N switching device comprises a III-N transistor comprising a source and a drain coupled to second and third leads of the electronic package, and wherein the electronic package includes a fourth lead coupled to the source for directly coupling of the source to a gate driver.

27 . The electronic component of claim 21 , wherein the III-N switching device comprises an enhancement mode III-N transistor.

28 . The electronic component of claim 27 , the electronic package further comprising a conductive structural base, wherein the enhancement mode III-N transistor is a lateral III-N transistor, the gate is a gate of the enhancement mode III-N transistor, and a source or a drain of the enhancement mode III-N transistor is electrically connected to the conductive struc

Assignees

• Transphorm Inc

Inventors

• Wang Zhan
• Wu Yifeng
• Honea James

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title