Integrated Power Assembly with Reduced Form Factor and Enhanced Thermal Dissipation

Patent metadata

Field	Value
Publication number	US-2016172279-A1
Application number	US-201514938671-A
Country	US
Kind code	A1
Filing date	Nov 11, 2015
Priority date	Dec 10, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

An integrated power assembly is disclosed. The integrated power assembly includes a printed circuit board, a first leadframe having partially etched segments and non-etched segments on the printed circuit board, a first semiconductor die configured for attachment to the partially etched segments of the first leadframe, a second leadframe having a legless conductive clip, and a second semiconductor die situated over the first semiconductor die and being coupled to the first semiconductor die by the legless conductive clip.

First claim

1 . An integrated power assembly comprising:
a printed circuit board; a first leadframe having partially etched segments and non-etched segments on said printed circuit board; a first semiconductor die configured for attachment to said partially etched segments of said first leadframe; a second leadframe having a legless conductive clip; a second semiconductor die situated over said first semiconductor die and being coupled to said first semiconductor die by said legless conductive clip.

2 . The integrated power assembly of claim 1 , wherein said second semiconductor die is coupled to said printed circuit board by a partially etched conductive clip of said second leadframe and at least one of said non-etched segments of said first leadframe.

3 . The integrated power assembly of claim 1 , wherein a drain electrode on said first semiconductor die is coupled to a source electrode on said second semiconductor die through said legless conductive clip.

4 . The integrated power assembly of claim 1 , wherein said first semiconductor die includes a first power transistor having a source electrode and a gate electrode at a bottom surface of said first semiconductor die, and a drain electrode on a top surface of said first semiconductor die.

5 . The integrated power assembly of claim 1 , wherein said second semiconductor die includes a second power transistor having a source electrode and a gate electrode at a bottom surface of said second semiconductor die, and a drain electrode on a top surface of said second semiconductor die.

6 . The integrated power assembly of claim 1 , wherein said second semiconductor die includes a second power transistor having a source electrode at a bottom surface of said second semiconductor die, and a drain electrode and a gate electrode on a top surface of said second semiconductor die.

7 . The integrated power assembly of claim 1 , wherein said first semiconductor die includes a first power transistor, and said second semiconductor die includes a second power transistor.

8 . The integrated power assembly of claim 7 , wherein at least one of said first power transistor and said second power transistor includes silicon.

9 . The integrated power assembly of claim 7 , wherein at least one of said first power transistor and said second power transistor includes gallium nitride (GaN).

10 . The integrated power assembly of claim 1 , wherein said first semiconductor die includes a synchronous transistor, and said second semiconductor die includes a control transistor coupled to said synchronous transistor in a half-bridge.

11 . The integrated power assembly of claim 1 , wherein said first semiconductor die includes a group IV transistor, and said second semiconductor die includes a group III-V transistor in cascode with said group IV transistor.

12 . An integrated power assembly comprising:
a printed circuit board; a first leadframe having partially etched segments and non-etched segments on said printed circuit board; a first semiconductor die having a first power switch configured for attachment to said partially etched segments of said first leadframe; a second leadframe having a legless conductive clip; a second semiconductor die having a second power switch situated over said first semiconductor die, wherein a source electrode of said second power switch is coupled to a drain electrode of said first power switch by said legless conductive clip.

13 . The integrated power assembly of claim 12 , wherein said second semiconductor die is coupled to said printed circuit board by a partially etched conductive clip of said second leadframe and at least one of said non-etched segments of said first leadframe.

14 . The integrated power assembly of claim 12 , wherein at least one of said first power switch and said second power switch includes silicon.

15 . The integrated power assembly of claim 12 , wherein at least one of said first power switch and said second power switch includes gallium nitride (GaN).

16 . The integrated power assembly of claim 12 , said first power switch includes a synchronous transistor, and said second power switch includes a control transistor coupled to said synchronous transistor in a half-bridge.

17 . The integrated power assembly of claim 12 , wherein at least one of said first power switch and said second power switch is selected from the group consisting of a field-effect transistor (FET), an insulated gate bipolar transistor (IGBT) and a high electron mobility transistor (HEMT).

18 . The integrated power assembly of claim 12 , wherein at least one of said first power switch and said second power switch includes a silicon FET or a GaN FET.

19 . The integrated power assembly of claim 12 , wherein said partially etched segments of said first leadframe have a substantially uniform thickness.

20 . The integrated power assembly of claim 12 , wherein said legless conductive clip includes copper.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07636

  Soldering or alloying · CPC title

• H10W72/652

  comprising metals or metalloids, e.g. silver · CPC title

• H10W90/811 Primary

  Multiple chips on leadframes · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title