Semiconductor device and fabrication method for semiconductor device

Patent metadata

Field	Value
Publication number	US-12009268-B2
Application number	US-202318352285-A
Country	US
Kind code	B2
Filing date	Jul 14, 2023
Priority date	Jun 17, 2019
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A semiconductor device includes trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate, a first conductivity type lower surface region provided in a part of a lower surface of the semiconductor substrate, a second conductivity type base region provided on the upper surface side, a first conductivity type first region disposed between the base region and the lower surface region, a first conductivity type upper surface region provided on an upper surface of the semiconductor substrate, and a second conductivity type bottom region disposed continuously in the first direction to be in contact with bottom portions of the trench portions. In a cross section along the first direction and perpendicular to the upper and lower surfaces and passing through the lower surface region, one end portion of the bottom region in the first direction locates directly above the lower surface region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate;
a first lower surface region of a first conductivity type provided in at least a part of a lower surface of the semiconductor substrate;
a base region of a second conductivity type provided on the upper surface side of the semiconductor substrate;
a first region of the first conductivity type provided in the semiconductor substrate and disposed between the base region and the first lower surface region in a depth direction of the semiconductor substrate;
a first upper surface region of the first conductivity type provided on an upper surface of the semiconductor substrate; and
a first bottom region of the second conductivity type provided in the semiconductor substrate and disposed continuously in the first direction such that the first bottom region is in contact with bottom portions of the plurality of trench portions, wherein
in a cross section that (i) is along the first direction and perpendicular to the upper surface and the lower surface of the semiconductor substrate and (ii) passes through the first lower surface region, one end portion of the first bottom region in the first direction locates directly above the first lower surface region in the depth direction.

2. The semiconductor device according to claim 1 , wherein
the cross section passes through the first upper surface region.

3. The semiconductor device according to claim 2 , further comprising:
a second upper surface region of the second conductivity type that is provided on the upper surface of the semiconductor substrate and has a doping concentration higher than a doping concentration of the base region, wherein
the first upper surface region has a doping concentration higher than a doping concentration of the first region.

4. The semiconductor device according to claim 1 , further comprising:
an edge terminal structure portion provided, in a top view, on a side of end sides of the semiconductor device; and
a well region of the second conductivity type disposed, in the top view, between the base region and the edge terminal structure portion, wherein
an other end portion of the first bottom region in the first direction is separated away from the well region.

5. The semiconductor device according to claim 4 , wherein
the first bottom region is electrically floating.

6. The semiconductor device according to claim 4 , wherein
the edge terminal structure portion includes a plurality of guard rings.

7. The semiconductor device according to claim 5 , further comprising:
a second lower surface region of the second conductivity type disposed in at least a part of the lower surface of the semiconductor substrate.

8. The semiconductor device according to claim 7 , further comprising:
a diode portion that includes the first lower surface region; and
a transistor portion that includes the second lower surface region, wherein
the first bottom region is provided across the transistor portion and the diode portion.

9. The semiconductor device according to claim 8 , wherein
the other end portion of the first bottom region faces the well region and is located in the transistor portion, and
the one end portion of the first bottom region faces opposite to the well region and is located in the diode portion.

10. The semiconductor device according to claim 8 , wherein
each of the plurality of trench portions includes a linear part extending in a second direction substantially perpendicular to the first direction in the top view, and
the diode portion and the transistor portion each have a longitudinal side in the second direction.

11. The semiconductor device according to claim 10 , wherein
the diode portion and the transistor portion are alternately arranged in the first direction in the top view.

12. The semiconductor device according to claim 1 , wherein
the plurality of trench portions include one or more gate trench portions and one or more dummy trench portions, and
the first bottom region is disposed continuously in the first direction such that the first bottom region is in contact with bottom portions of the one or more gate trench portions and the one or more dummy trench portions.

13. The semiconductor device according to claim 1 , further comprising:
an accumulation region of the first conductivity type disposed between the base region and the first bottom region in the depth direction.

14. The semiconductor device according to claim 13 , wherein
the accumulation region has a doping concentration higher than a doping concentration of the first region and is in contact with an upper surface of the first bottom region.

15. The semiconductor device according to claim 1 , further comprising:
a buffer region of the first conductivity type disposed between the first region and the first lower surface region in the depth direction.

16. The semiconductor device according to claim 1 , further comprising:
a second bottom region of the second conductivity type in contact with a lower surface of the first bottom region.

17. The semiconductor device according to claim 16 , wherein
in the cross section, the one end portion of the first bottom region in the first direction extend outside of corresponding end portion of the second bottom region in the first direction.

18. The semiconductor device according to claim 16 , wherein
a doping concentration of the second bottom region is lower than a doping concentration of the first bottom region.

19. The semiconductor device according to claim 16 , wherein
a doping concentration of the second bottom region is the same as a doping concentration of a bulk doping region of the semiconductor substrate.

20. The semiconductor device according to claim 1 , wherein
a donor concentration of the first region is higher than a doping concentration of a bulk doping region of the semiconductor substrate.

Assignees

• Fuji Electric Co Ltd

Inventors

• Kubouchi Motoyoshi
• Yoshida Kosuke
• Yoshida Soichi
• Yoshikawa Koh
• Suganuma Nao

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/18

  Diffusion lifetime killers · CPC title

• H10P30/214

  Recoil-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title